exp3-13.tst

verilog大量源程序

/*   2-1 SELECTOR_TEST   */
`timescale	1ns/1ns
   module	SEL_TEST;
   reg	[1:0] IN;
   reg	SEL_IN;
   wire	F;

	SEL	SEL	( IN[0], IN[1], SEL_IN, F );
	always	#150	SEL_IN = ~SEL_IN;
	always	 #50	IN = IN + 1;
	initial	begin
	   SEL_IN = 0; IN = 0;
	   #450	$finish;
	end
endmodule