exp3-21.v

来自「verilog大量源程序」· Verilog 代码 · 共 28 行

/*  Data Difinision	*/
`define	   SW_IN0     4'b0001
`define	   SW_IN1     4'b0010
`define	   SW_IN2     4'b0100
`define	   SW_IN3     4'b1000

/*	ENCORDER	*/
module	ENC	( IN, Y );
    input	[3:0]	IN;
    output	[1:0]	Y;

    assign Y = FUNC_ENC ( IN );

    function	[1:0] FUNC_ENC;
       input	[3:0] IN;

	 case ( IN )
		`SW_IN0:FUNC_ENC = 0;
		`SW_IN1:FUNC_ENC = 1;
		`SW_IN2:FUNC_ENC = 2;
		`SW_IN3:FUNC_ENC = 3;

	endcase
endfunction

endmodule