exp3-01.v

来自「verilog大量源程序」· Verilog 代码 · 共 12 行

/*	2-1 SELECTOR	*/
module	SEL	( A, B, SEL, F );
   input	A, B, SEL;
   output	F;
   wire	SEL_NOT, AND1, AND2;
	   
   not	U1	( SEL_NOT, SEL );
   and	U2	( AND1, B, SEL ),
       U3	( AND2, A, SEL_NOT );
   or	 U4	( F , AND1, AND2 );
endmodule