exp3-10.v

来自「verilog大量源程序」· Verilog 代码 · 共 21 行

/*	4-1 SELECTOR	*/
module	SEL	( A, B, C, D, SEL, F );
   input	A, B, C, D;
   input	[1:0] SEL;
   output	F;

	 assign	F= SEL4_1_FUNC ( A, B, C, D, SEL );

   function	SEL4_1_FUNC;
      input	A, B, C, D;
      input	[1:0] SEL;
	
      case ( SEL )
		   0:SEL4_1_FUNC = A;
		   1:SEL4_1_FUNC = B;
		   2:SEL4_1_FUNC = C;
		   3:SEL4_1_FUNC = D;
	   endcase
   endfunction
endmodule