backward.sum

verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.

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Cell: backward    View: INTERFACE    Library: work

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Total accumulated area : 

 Number of ports :                       0
 Number of nets :                        0
 Number of instances :                   0
 Number of references to this view :     0






                        Slack Table at End Points


End points                         Slack       Arrival             Required
                                             rise     fall      rise     fall




                        Critical Path Report

There are no paths that violate user specified options or constraints