backward.v

来自「verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.」· Verilog 代码 · 共 17 行

module backward;
reg [0:2] backwards_reg;	
reg [2:0] test;
/*	{1'b0, test, 8'h55} is the same as:

{1'b0, test[2], test[1], test[0], 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1} */
	always @ (test)
	begin
	test		=	backwards_reg;
// The assignment above is equivalent to the assignments below:
	test[2]	=	backwards_reg[0];
	test[1]	=	backwards_reg[1];
	test[0]	=	backwards_reg[2];
	end
endmodule