dds_hier_info

程序用VHDL实现： 频率合成

|dds
OUT_C[0] <= LMP_DFF_10:inst7.q[0]
OUT_C[1] <= LMP_DFF_10:inst7.q[1]
OUT_C[2] <= LMP_DFF_10:inst7.q[2]
OUT_C[3] <= LMP_DFF_10:inst7.q[3]
OUT_C[4] <= LMP_DFF_10:inst7.q[4]
OUT_C[5] <= LMP_DFF_10:inst7.q[5]
OUT_C[6] <= LMP_DFF_10:inst7.q[6]
OUT_C[7] <= LMP_DFF_10:inst7.q[7]
OUT_C[8] <= LMP_DFF_10:inst7.q[8]
OUT_C[9] <= LMP_DFF_10:inst7.q[9]
CLK => LMP_DFF_10:inst7.clock
CLK => LPM_ROM_10:inst3.inclock
CLK => LPM_DFF:inst1.clock
CLK => LMP_DFF_10:inst8.clock
CLK => LPM_ROM_10:inst2.inclock
FREQ[0] => LPM_ADDER_10:inst.datab[0]
FREQ[1] => LPM_ADDER_10:inst.datab[1]
FREQ[2] => LPM_ADDER_10:inst.datab[2]
FREQ[3] => LPM_ADDER_10:inst.datab[3]
FREQ[4] => LPM_ADDER_10:inst.datab[4]
FREQ[5] => LPM_ADDER_10:inst.datab[5]
FREQ[6] => LPM_ADDER_10:inst.datab[6]
FREQ[7] => LPM_ADDER_10:inst.datab[7]
FREQ[8] => LPM_ADDER_10:inst.datab[8]
FREQ[9] => LPM_ADDER_10:inst.datab[9]
PHASE[0] => LPM_ADDER_10:inst6.datab[0]
PHASE[1] => LPM_ADDER_10:inst6.datab[1]
PHASE[2] => LPM_ADDER_10:inst6.datab[2]
PHASE[3] => LPM_ADDER_10:inst6.datab[3]
PHASE[4] => LPM_ADDER_10:inst6.datab[4]
PHASE[5] => LPM_ADDER_10:inst6.datab[5]
PHASE[6] => LPM_ADDER_10:inst6.datab[6]
PHASE[7] => LPM_ADDER_10:inst6.datab[7]
PHASE[8] => LPM_ADDER_10:inst6.datab[8]
PHASE[9] => LPM_ADDER_10:inst6.datab[9]
OUT_S[0] <= LMP_DFF_10:inst8.q[0]
OUT_S[1] <= LMP_DFF_10:inst8.q[1]
OUT_S[2] <= LMP_DFF_10:inst8.q[2]
OUT_S[3] <= LMP_DFF_10:inst8.q[3]
OUT_S[4] <= LMP_DFF_10:inst8.q[4]
OUT_S[5] <= LMP_DFF_10:inst8.q[5]
OUT_S[6] <= LMP_DFF_10:inst8.q[6]
OUT_S[7] <= LMP_DFF_10:inst8.q[7]
OUT_S[8] <= LMP_DFF_10:inst8.q[8]
OUT_S[9] <= LMP_DFF_10:inst8.q[9]


|dds|LMP_DFF_10:inst7
clock => lpm_ff:lpm_ff_component.clock
aload => lpm_ff:lpm_ff_component.aload
aset => lpm_ff:lpm_ff_component.aset
data[0] => lpm_ff:lpm_ff_component.data[0]
data[1] => lpm_ff:lpm_ff_component.data[1]
data[2] => lpm_ff:lpm_ff_component.data[2]
data[3] => lpm_ff:lpm_ff_component.data[3]
data[4] => lpm_ff:lpm_ff_component.data[4]
data[5] => lpm_ff:lpm_ff_component.data[5]
data[6] => lpm_ff:lpm_ff_component.data[6]
data[7] => lpm_ff:lpm_ff_component.data[7]
data[8] => lpm_ff:lpm_ff_component.data[8]
data[9] => lpm_ff:lpm_ff_component.data[9]
q[0] <= lpm_ff:lpm_ff_component.q[0]
q[1] <= lpm_ff:lpm_ff_component.q[1]
q[2] <= lpm_ff:lpm_ff_component.q[2]
q[3] <= lpm_ff:lpm_ff_component.q[3]
q[4] <= lpm_ff:lpm_ff_component.q[4]
q[5] <= lpm_ff:lpm_ff_component.q[5]
q[6] <= lpm_ff:lpm_ff_component.q[6]
q[7] <= lpm_ff:lpm_ff_component.q[7]
q[8] <= lpm_ff:lpm_ff_component.q[8]
q[9] <= lpm_ff:lpm_ff_component.q[9]


|dds|LMP_DFF_10:inst7|lpm_ff:lpm_ff_component
clock => dffs[9].CLK
clock => dffs[8].CLK
clock => dffs[7].CLK
clock => dffs[6].CLK
clock => dffs[5].CLK
clock => dffs[4].CLK
clock => dffs[3].CLK
clock => dffs[2].CLK
clock => dffs[1].CLK
clock => dffs[0].CLK
enable => dffs[9].ENA
enable => dffs[8].ENA
enable => dffs[7].ENA
enable => dffs[6].ENA
enable => dffs[5].ENA
enable => dffs[4].ENA
enable => dffs[3].ENA
enable => dffs[2].ENA
enable => dffs[1].ENA
enable => dffs[0].ENA
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffs[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffs[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffs[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffs[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= dffs[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= dffs[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= dffs[7].DB_MAX_OUTPUT_PORT_TYPE
q[8] <= dffs[8].DB_MAX_OUTPUT_PORT_TYPE
q[9] <= dffs[9].DB_MAX_OUTPUT_PORT_TYPE


|dds|LPM_ROM_10:inst3
address[0] => lpm_rom:lpm_rom_component.address[0]
address[1] => lpm_rom:lpm_rom_component.address[1]
address[2] => lpm_rom:lpm_rom_component.address[2]
address[3] => lpm_rom:lpm_rom_component.address[3]
address[4] => lpm_rom:lpm_rom_component.address[4]
address[5] => lpm_rom:lpm_rom_component.address[5]
address[6] => lpm_rom:lpm_rom_component.address[6]
address[7] => lpm_rom:lpm_rom_component.address[7]
address[8] => lpm_rom:lpm_rom_component.address[8]
address[9] => lpm_rom:lpm_rom_component.address[9]
inclock => lpm_rom:lpm_rom_component.inclock
q[0] <= lpm_rom:lpm_rom_component.q[0]
q[1] <= lpm_rom:lpm_rom_component.q[1]
q[2] <= lpm_rom:lpm_rom_component.q[2]
q[3] <= lpm_rom:lpm_rom_component.q[3]
q[4] <= lpm_rom:lpm_rom_component.q[4]
q[5] <= lpm_rom:lpm_rom_component.q[5]
q[6] <= lpm_rom:lpm_rom_component.q[6]
q[7] <= lpm_rom:lpm_rom_component.q[7]
q[8] <= lpm_rom:lpm_rom_component.q[8]
q[9] <= lpm_rom:lpm_rom_component.q[9]


|dds|LPM_ROM_10:inst3|lpm_rom:lpm_rom_component
address[0] => altrom:srom.address[0]
address[1] => altrom:srom.address[1]
address[2] => altrom:srom.address[2]
address[3] => altrom:srom.address[3]
address[4] => altrom:srom.address[4]
address[5] => altrom:srom.address[5]
address[6] => altrom:srom.address[6]
address[7] => altrom:srom.address[7]
address[8] => altrom:srom.address[8]
address[9] => altrom:srom.address[9]
inclock => altrom:srom.clocki
memenab => otri[9].OE
memenab => otri[8].OE
memenab => otri[7].OE
memenab => otri[6].OE
memenab => otri[5].OE
memenab => otri[4].OE
memenab => otri[3].OE
memenab => otri[2].OE
memenab => otri[1].OE
memenab => otri[0].OE
q[0] <= otri[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= otri[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= otri[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= otri[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= otri[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= otri[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= otri[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= otri[7].DB_MAX_OUTPUT_PORT_TYPE
q[8] <= otri[8].DB_MAX_OUTPUT_PORT_TYPE
q[9] <= otri[9].DB_MAX_OUTPUT_PORT_TYPE


|dds|LPM_ROM_10:inst3|lpm_rom:lpm_rom_component|altrom:srom
address[0] => segment[0][9].WADDR
address[0] => segment[0][9].RADDR
address[0] => segment[0][8].WADDR
address[0] => segment[0][8].RADDR
address[0] => segment[0][7].WADDR
address[0] => segment[0][7].RADDR
address[0] => segment[0][6].WADDR
address[0] => segment[0][6].RADDR
address[0] => segment[0][5].WADDR
address[0] => segment[0][5].RADDR
address[0] => segment[0][4].WADDR
address[0] => segment[0][4].RADDR
address[0] => segment[0][3].WADDR
address[0] => segment[0][3].RADDR
address[0] => segment[0][2].WADDR
address[0] => segment[0][2].RADDR
address[0] => segment[0][1].WADDR
address[0] => segment[0][1].RADDR
address[0] => segment[0][0].WADDR
address[0] => segment[0][0].RADDR
address[1] => segment[0][9].WADDR1
address[1] => segment[0][9].RADDR1
address[1] => segment[0][8].WADDR1
address[1] => segment[0][8].RADDR1
address[1] => segment[0][7].WADDR1
address[1] => segment[0][7].RADDR1
address[1] => segment[0][6].WADDR1
address[1] => segment[0][6].RADDR1
address[1] => segment[0][5].WADDR1
address[1] => segment[0][5].RADDR1
address[1] => segment[0][4].WADDR1
address[1] => segment[0][4].RADDR1
address[1] => segment[0][3].WADDR1
address[1] => segment[0][3].RADDR1
address[1] => segment[0][2].WADDR1
address[1] => segment[0][2].RADDR1
address[1] => segment[0][1].WADDR1
address[1] => segment[0][1].RADDR1
address[1] => segment[0][0].WADDR1
address[1] => segment[0][0].RADDR1
address[2] => segment[0][9].WADDR2
address[2] => segment[0][9].RADDR2
address[2] => segment[0][8].WADDR2
address[2] => segment[0][8].RADDR2
address[2] => segment[0][7].WADDR2
address[2] => segment[0][7].RADDR2
address[2] => segment[0][6].WADDR2
address[2] => segment[0][6].RADDR2
address[2] => segment[0][5].WADDR2
address[2] => segment[0][5].RADDR2
address[2] => segment[0][4].WADDR2
address[2] => segment[0][4].RADDR2
address[2] => segment[0][3].WADDR2
address[2] => segment[0][3].RADDR2
address[2] => segment[0][2].WADDR2
address[2] => segment[0][2].RADDR2
address[2] => segment[0][1].WADDR2
address[2] => segment[0][1].RADDR2
address[2] => segment[0][0].WADDR2
address[2] => segment[0][0].RADDR2
address[3] => segment[0][9].WADDR3
address[3] => segment[0][9].RADDR3
address[3] => segment[0][8].WADDR3
address[3] => segment[0][8].RADDR3
address[3] => segment[0][7].WADDR3
address[3] => segment[0][7].RADDR3
address[3] => segment[0][6].WADDR3
address[3] => segment[0][6].RADDR3
address[3] => segment[0][5].WADDR3
address[3] => segment[0][5].RADDR3
address[3] => segment[0][4].WADDR3
address[3] => segment[0][4].RADDR3
address[3] => segment[0][3].WADDR3
address[3] => segment[0][3].RADDR3
address[3] => segment[0][2].WADDR3
address[3] => segment[0][2].RADDR3
address[3] => segment[0][1].WADDR3
address[3] => segment[0][1].RADDR3
address[3] => segment[0][0].WADDR3
address[3] => segment[0][0].RADDR3
address[4] => segment[0][9].WADDR4
address[4] => segment[0][9].RADDR4
address[4] => segment[0][8].WADDR4
address[4] => segment[0][8].RADDR4
address[4] => segment[0][7].WADDR4
address[4] => segment[0][7].RADDR4
address[4] => segment[0][6].WADDR4
address[4] => segment[0][6].RADDR4
address[4] => segment[0][5].WADDR4
address[4] => segment[0][5].RADDR4
address[4] => segment[0][4].WADDR4
address[4] => segment[0][4].RADDR4
address[4] => segment[0][3].WADDR4
address[4] => segment[0][3].RADDR4
address[4] => segment[0][2].WADDR4
address[4] => segment[0][2].RADDR4
address[4] => segment[0][1].WADDR4
address[4] => segment[0][1].RADDR4
address[4] => segment[0][0].WADDR4
address[4] => segment[0][0].RADDR4
address[5] => segment[0][9].WADDR5
address[5] => segment[0][9].RADDR5
address[5] => segment[0][8].WADDR5
address[5] => segment[0][8].RADDR5
address[5] => segment[0][7].WADDR5
address[5] => segment[0][7].RADDR5
address[5] => segment[0][6].WADDR5
address[5] => segment[0][6].RADDR5
address[5] => segment[0][5].WADDR5
address[5] => segment[0][5].RADDR5
address[5] => segment[0][4].WADDR5
address[5] => segment[0][4].RADDR5
address[5] => segment[0][3].WADDR5
address[5] => segment[0][3].RADDR5
address[5] => segment[0][2].WADDR5
address[5] => segment[0][2].RADDR5
address[5] => segment[0][1].WADDR5
address[5] => segment[0][1].RADDR5
address[5] => segment[0][0].WADDR5
address[5] => segment[0][0].RADDR5
address[6] => segment[0][9].WADDR6
address[6] => segment[0][9].RADDR6
address[6] => segment[0][8].WADDR6
address[6] => segment[0][8].RADDR6
address[6] => segment[0][7].WADDR6
address[6] => segment[0][7].RADDR6
address[6] => segment[0][6].WADDR6
address[6] => segment[0][6].RADDR6
address[6] => segment[0][5].WADDR6
address[6] => segment[0][5].RADDR6
address[6] => segment[0][4].WADDR6
address[6] => segment[0][4].RADDR6
address[6] => segment[0][3].WADDR6
address[6] => segment[0][3].RADDR6
address[6] => segment[0][2].WADDR6
address[6] => segment[0][2].RADDR6
address[6] => segment[0][1].WADDR6
address[6] => segment[0][1].RADDR6
address[6] => segment[0][0].WADDR6
address[6] => segment[0][0].RADDR6
address[7] => segment[0][9].WADDR7
address[7] => segment[0][9].RADDR7
address[7] => segment[0][8].WADDR7
address[7] => segment[0][8].RADDR7
address[7] => segment[0][7].WADDR7
address[7] => segment[0][7].RADDR7
address[7] => segment[0][6].WADDR7
address[7] => segment[0][6].RADDR7
address[7] => segment[0][5].WADDR7
address[7] => segment[0][5].RADDR7
address[7] => segment[0][4].WADDR7
address[7] => segment[0][4].RADDR7
address[7] => segment[0][3].WADDR7
address[7] => segment[0][3].RADDR7
address[7] => segment[0][2].WADDR7
address[7] => segment[0][2].RADDR7
address[7] => segment[0][1].WADDR7
address[7] => segment[0][1].RADDR7
address[7] => segment[0][0].WADDR7
address[7] => segment[0][0].RADDR7
address[8] => segment[0][9].WADDR8
address[8] => segment[0][9].RADDR8
address[8] => segment[0][8].WADDR8
address[8] => segment[0][8].RADDR8
address[8] => segment[0][7].WADDR8
address[8] => segment[0][7].RADDR8