dds.tan.rpt

程序用VHDL实现： 频率合成

; Device name                                           ; EP1K30TC144-3      ;      ;    ;
; Report IO Paths Separately                            ; Off                ;      ;    ;
; Ignore user-defined clock settings                    ; Off                ;      ;    ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;
; Cut off read during write signal paths                ; On                 ;      ;    ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;
; Run Minimum Analysis                                  ; On                 ;      ;    ;
; Use Minimum Timing Models                             ; Off                ;      ;    ;
; Number of paths to report                             ; 200                ;      ;    ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;
+-------------------------------------------------------+--------------------+------+----+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                    ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Type                   ; Slack ; Required Time ; Actual Time                      ; From                                             ; To                                                                  ;
+------------------------+-------+---------------+----------------------------------+--------------------------------------------------+---------------------------------------------------------------------+
; Worst-case tsu         ; N/A   ; None          ; 13.500 ns                        ; FREQ[0]                                          ; LPM_DFF:inst1|lpm_ff:lpm_ff_component|dffs[9]                       ;
; Worst-case tco         ; N/A   ; None          ; 11.500 ns                        ; LMP_DFF_10:inst7|lpm_ff:lpm_ff_component|dffs[0] ; OUT_C[0]                                                            ;
; Worst-case th          ; N/A   ; None          ; -3.100 ns                        ; PHASE[9]                                         ; LPM_ROM_10:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra9 ;
; Worst-case minimum tco ; N/A   ; None          ; 9.900 ns                         ; LMP_DFF_10:inst7|lpm_ff:lpm_ff_component|dffs[4] ; OUT_C[4]                                                            ;
; Clock Setup: 'CLK'     ; N/A   ; None          ; 96.15 MHz ( period = 10.400 ns ) ; LPM_DFF:inst1|lpm_ff:lpm_ff_component|dffs[0]    ; LPM_ROM_10:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra9 ;
+------------------------+-------+---------------+----------------------------------+--------------------------------------------------+---------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+---------------------------------------------------------------------------------------------------------------------------------------
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; CLK             ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                                                                                                                                                                                           ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Slack                                   ; Actual fmax (period)                                       ; From                                                                ; To                                                                  ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+------------------------------------------------------------+---------------------------------------------------------------------+---------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 96.15 MHz ( period = 10.400 ns )                           ; LPM_DFF:inst1|lpm_ff:lpm_ff_component|dffs[0]                       ; LPM_ROM_10:inst2|lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra9 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 96.15 MHz ( period = 10.400 ns )                           ; LPM_DFF:inst1|lpm_ff:lpm_ff_component|dffs[0]                       ; LPM_ROM_10:inst2|lpm_rom:lpm_rom_component|altrom:srom|q[2]~reg_ra9 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 96.15 MHz ( period = 10.400 ns )                           ; LPM_DFF:inst1|lpm_ff:lpm_ff_component|dffs[0]                       ; LPM_ROM_10:inst2|lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra9 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 96.15 MHz ( period = 10.400 ns )                           ; LPM_DFF:inst1|lpm_ff:lpm_ff_component|dffs[0]                       ; LPM_ROM_10:inst2|lpm_rom:lpm_rom_component|altrom:srom|q[5]~reg_ra9 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 96.15 MHz ( period = 10.400 ns )                           ; LPM_DFF:inst1|lpm_ff:lpm_ff_component|dffs[0]                       ; LPM_ROM_10:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra9 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 96.15 MHz ( period = 10.400 ns )                           ; LPM_DFF:inst1|lpm_ff:lpm_ff_component|dffs[0]                       ; LPM_ROM_10:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra9 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 97.09 MHz ( period = 10.300 ns )                           ; LPM_DFF:inst1|lpm_ff:lpm_ff_component|dffs[0]                       ; LPM_ROM_10:inst2|lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra9 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 97.09 MHz ( period = 10.300 ns )                           ; LPM_DFF:inst1|lpm_ff:lpm_ff_component|dffs[0]                       ; LPM_ROM_10:inst2|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra9 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;