dds.tan.summary

程序用VHDL实现： 频率合成

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 13.500 ns
From           : FREQ[0]
To             : LPM_DFF:inst1|lpm_ff:lpm_ff_component|dffs[9]

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 11.500 ns
From           : LMP_DFF_10:inst7|lpm_ff:lpm_ff_component|dffs[0]
To             : OUT_C[0]

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -3.100 ns
From           : PHASE[9]
To             : LPM_ROM_10:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra9

Type           : Worst-case minimum tco
Slack          : N/A
Required Time  : None
Actual Time    : 9.900 ns
From           : LMP_DFF_10:inst7|lpm_ff:lpm_ff_component|dffs[4]
To             : OUT_C[4]

Type           : Clock Setup: 'CLK'
Slack          : N/A
Required Time  : None
Actual Time    : 96.15 MHz ( period = 10.400 ns )
From           : LPM_DFF:inst1|lpm_ff:lpm_ff_component|dffs[0]
To             : LPM_ROM_10:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra9

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