dds.map.rpt

程序用VHDL实现： 频率合成

;    |LPM_ROM_10:inst2|                     ; 0 (0)       ; 0         ; 10240       ; 0    ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |dds|LPM_ROM_10:inst2                                                                           ;
;       |lpm_rom:lpm_rom_component|         ; 0 (0)       ; 0         ; 10240       ; 0    ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |dds|LPM_ROM_10:inst2|lpm_rom:lpm_rom_component                                                 ;
;          |altrom:srom|                    ; 0 (0)       ; 0         ; 10240       ; 0    ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |dds|LPM_ROM_10:inst2|lpm_rom:lpm_rom_component|altrom:srom                                     ;
;    |LPM_ROM_10:inst3|                     ; 0 (0)       ; 0         ; 10240       ; 0    ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |dds|LPM_ROM_10:inst3                                                                           ;
;       |lpm_rom:lpm_rom_component|         ; 0 (0)       ; 0         ; 10240       ; 0    ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |dds|LPM_ROM_10:inst3|lpm_rom:lpm_rom_component                                                 ;
;          |altrom:srom|                    ; 0 (0)       ; 0         ; 10240       ; 0    ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |dds|LPM_ROM_10:inst3|lpm_rom:lpm_rom_component|altrom:srom                                     ;
+-------------------------------------------+-------------+-----------+-------------+------+--------------+-------------------+------------------+-----------------+-------------------------------------------------------------------------------------------------+


+---------------------------------+
; Analysis & Synthesis Equations  ;
+---------------------------------+
The equations can be found in D:/xiongxusheng/eda/pinglvhecheng/dds.map.eqn.


+-----------------------------------------------------------+
; Analysis & Synthesis Files Read                           ;
+------------------------------------------------------------
; File Name                                          ; Read ;
+----------------------------------------------------+------+
; dds.bdf                                            ; Read ;
; D:/xiongxusheng/eda/pinglvhecheng/LMP_DFF_10.vhd   ; Read ;
; c:/quartus/libraries/megafunctions/lpm_ff.tdf      ; Read ;
; D:/xiongxusheng/eda/pinglvhecheng/LPM_ROM_10.vhd   ; Read ;
; c:/quartus/libraries/megafunctions/lpm_rom.tdf     ; Read ;
; c:/quartus/libraries/megafunctions/altrom.tdf      ; Read ;
; D:/xiongxusheng/eda/pinglvhecheng/LPM_ADDER_10.vhd ; Read ;
; c:/quartus/libraries/megafunctions/lpm_add_sub.tdf ; Read ;
; c:/quartus/libraries/megafunctions/addcore.tdf     ; Read ;
; c:/quartus/libraries/megafunctions/a_csnbuffer.tdf ; Read ;
; c:/quartus/libraries/megafunctions/altshift.tdf    ; Read ;
; D:/xiongxusheng/eda/pinglvhecheng/LPM_DFF.vhd      ; Read ;
+----------------------------------------------------+------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------------------------------
; Resource                      ; Usage       ;
+-------------------------------+-------------+
; Logic cells                   ; 50          ;
; Total combinational functions ; 20          ;
; Total registers               ; 30          ;
; I/O pins                      ; 41          ;
; Total memory bits             ; 20480       ;
; Maximum fan-out node          ; CLK         ;
; Maximum fan-out               ; 50          ;
; Total fan-out                 ; 358         ;
; Average fan-out               ; 3.23        ;
+-------------------------------+-------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                        ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------
; Name                                                           ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size  ; MIF         ;
+----------------------------------------------------------------+------+--------------+--------------+--------------+--------------+-------+-------------+
; LPM_ROM_10:inst2|lpm_rom:lpm_rom_component|altrom:srom|content ; ROM  ; 1024         ; 10           ; --           ; --           ; 10240 ; sin_rom.mif ;
; LPM_ROM_10:inst3|lpm_rom:lpm_rom_component|altrom:srom|content ; ROM  ; 1024         ; 10           ; --           ; --           ; 10240 ; sin_rom.mif ;
+----------------------------------------------------------------+------+--------------+--------------+--------------+--------------+-------+-------------+


+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+-----------------------------------------------------------------
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 0     ;
; Number of synthesis-generated cells                    ; 50    ;
; Number of WYSIWYG LUTs                                 ; 0     ;
; Number of synthesis-generated LUTs                     ; 20    ;
; Number of WYSIWYG registers                            ; 0     ;
; Number of synthesis-generated registers                ; 30    ;
; Number of cells with combinational logic only          ; 20    ;
; Number of cells with registers only                    ; 30    ;
; Number of cells with combinational logic and registers ; 0     ;
+--------------------------------------------------------+-------+


+----------------------------------------------+
; General Register Statistics                  ;
+-----------------------------------------------
; Statistic                            ; Value ;
+--------------------------------------+-------+
; Number of registers using SCLR       ; 0     ;
; Number of registers using SLOAD      ; 0     ;
; Number of registers using ACLR       ; 0     ;
; Number of registers using ALOAD      ; 0     ;
; Number of registers using CLK_ENABLE ; 0     ;
; Number of registers using OE         ; 0     ;
; Number of registers using PRESET     ; 0     ;
+--------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Messages  ;
+--------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version
    Info: Processing started: Sun Jul 31 10:54:22 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off dds -c dds
Info: Found 1 design units and 1 entities in source file dds.bdf
    Info: Found entity 1: dds
Warning: Port aload of type LMP_DFF_10 and instance inst7 is missing source signal
Warning: Port aset of type LMP_DFF_10 and instance inst7 is missing source signal
Warning: Port cin of type LPM_ADDER_10 and instance inst6 is missing source signal
Warning: Port aload of type LPM_DFF and instance inst1 is missing source signal
Warning: Port aset of type LPM_DFF and instance inst1 is missing source signal
Warning: Port cin of type LPM_ADDER_10 and instance inst is missing source signal
Warning: Port aload of type LMP_DFF_10 and instance inst8 is missing source signal
Warning: Port aset of type LMP_DFF_10 and instance inst8 is missing source signal
Info: Using design file LMP_DFF_10.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: LMP_DFF_10-SYN
    Info: Found entity 1: LMP_DFF_10
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/lpm_ff.tdf
    Info: Found entity 1: lpm_ff
Info: Using design file LPM_ROM_10.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: LPM_ROM_10-SYN
    Info: Found entity 1: LPM_ROM_10
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/lpm_rom.tdf
    Info: Found entity 1: lpm_rom
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/altrom.tdf
    Info: Found entity 1: altrom
Info: Using design file LPM_ADDER_10.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: LPM_ADDER_10-SYN
    Info: Found entity 1: LPM_ADDER_10
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Warning: Entity LPM_DFF obtained from D:/xiongxusheng/eda/pinglvhecheng/LPM_DFF.vhd instead of from Quartus II megafunction library
Info: Using design file LPM_DFF.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: LPM_DFF-SYN
    Info: Found entity 1: LPM_DFF
Warning: Converted TRI buffer to OR gate or removed OPNDRN
    Warning: Converting TRI node LPM_ROM_10:inst3|lpm_rom:lpm_rom_component|otri[9] that feeds logic to an OR gate
    Warning: Converting TRI node LPM_ROM_10:inst3|lpm_rom:lpm_rom_component|otri[8] that feeds logic to an OR gate
    Warning: Converting TRI node LPM_ROM_10:inst3|lpm_rom:lpm_rom_component|otri[7] that feeds logic to an OR gate
    Warning: Converting TRI node LPM_ROM_10:inst3|lpm_rom:lpm_rom_component|otri[6] that feeds logic to an OR gate
    Warning: Converting TRI node LPM_ROM_10:inst3|lpm_rom:lpm_rom_component|otri[5] that feeds logic to an OR gate
    Warning: Converting TRI node LPM_ROM_10:inst3|lpm_rom:lpm_rom_component|otri[4] that feeds logic to an OR gate
    Warning: Converting TRI node LPM_ROM_10:inst3|lpm_rom:lpm_rom_component|otri[3] that feeds logic to an OR gate
    Warning: Converting TRI node LPM_ROM_10:inst3|lpm_rom:lpm_rom_component|otri[2] that feeds logic to an OR gate
    Warning: Converting TRI node LPM_ROM_10:inst3|lpm_rom:lpm_rom_component|otri[1] that feeds logic to an OR gate
    Warning: Converting TRI node LPM_ROM_10:inst3|lpm_rom:lpm_rom_component|otri[0] that feeds logic to an OR gate
    Warning: Converting TRI node LPM_ROM_10:inst2|lpm_rom:lpm_rom_component|otri[9] that feeds logic to an OR gate
    Warning: Converting TRI node LPM_ROM_10:inst2|lpm_rom:lpm_rom_component|otri[8] that feeds logic to an OR gate
    Warning: Converting TRI node LPM_ROM_10:inst2|lpm_rom:lpm_rom_component|otri[7] that feeds logic to an OR gate
    Warning: Converting TRI node LPM_ROM_10:inst2|lpm_rom:lpm_rom_component|otri[6] that feeds logic to an OR gate
    Warning: Converting TRI node LPM_ROM_10:inst2|lpm_rom:lpm_rom_component|otri[5] that feeds logic to an OR gate
    Warning: Converting TRI node LPM_ROM_10:inst2|lpm_rom:lpm_rom_component|otri[4] that feeds logic to an OR gate
    Warning: Converting TRI node LPM_ROM_10:inst2|lpm_rom:lpm_rom_component|otri[3] that feeds logic to an OR gate
    Warning: Converting TRI node LPM_ROM_10:inst2|lpm_rom:lpm_rom_component|otri[2] that feeds logic to an OR gate
    Warning: Converting TRI node LPM_ROM_10:inst2|lpm_rom:lpm_rom_component|otri[1] that feeds logic to an OR gate
    Warning: Converting TRI node LPM_ROM_10:inst2|lpm_rom:lpm_rom_component|otri[0] that feeds logic to an OR gate
Info: Implemented 111 device resources after synthesis - the final resource count might be different
    Info: Implemented 21 input pins
    Info: Implemented 20 output pins
    Info: Implemented 50 logic cells
    Info: Implemented 20 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 30 warnings
    Info: Processing ended: Sun Jul 31 10:54:28 2005
    Info: Elapsed time: 00:00:06