📄 frequ.tan.rpt
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Timing Analyzer report for frequ
Wed Aug 10 16:32:40 2005
Version 4.2 Build 157 12/07/2004 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tco
7. tpd
8. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+------+-----+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+------+-----+------------+----------+--------------+
; Worst-case tco ; N/A ; None ; 16.000 ns ; en ; clr ; clk ; ; 0 ;
; Worst-case tpd ; N/A ; None ; 12.900 ns ; clk ; clr ; ; ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; en ; en ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+------+-----+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EPF10K20TC144-4 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minumum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Clock Analysis Only ; Off ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off clear and preset signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Do Min/Max analysis using Rise/Fall delays ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Use Clock Latency for PLL offset ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; clk ; ; User Pin ; NONE ; NONE ; N/A ; N/A ; N/A ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+------+----+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+------+----+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; en ; en ; clk ; clk ; None ; None ; 1.800 ns ;
+-------+------------------------------------------------+------+----+------------+----------+-----------------------------+---------------------------+-------------------------+
+----------------------------------------------------------------+
; tco ;
+-------+--------------+------------+------+--------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+------+--------+------------+
; N/A ; None ; 16.000 ns ; en ; clr ; clk ;
; N/A ; None ; 13.100 ns ; en ; cnt_en ; clk ;
+-------+--------------+------------+------+--------+------------+
+----------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+-----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+-----+
; N/A ; None ; 12.900 ns ; clk ; clr ;
+-------+-------------------+-----------------+------+-----+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
Info: Processing started: Wed Aug 10 16:32:40 2005
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off frequ -c frequ
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 125.0 MHz between source register "en" and destination register "en"
Info: fmax restricted to Clock High delay (4.0 ns) plus Clock Low delay (4.0 ns) : restricted to 8.0 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 1.800 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_A21; Fanout = 3; REG Node = 'en'
Info: 2: + IC(0.600 ns) + CELL(1.200 ns) = 1.800 ns; Loc. = LC7_A21; Fanout = 3; REG Node = 'en'
Info: Total cell delay = 1.200 ns ( 66.67 % )
Info: Total interconnect delay = 0.600 ns ( 33.33 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clk" to destination register is 5.300 ns
Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 2; CLK Node = 'clk'
Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC7_A21; Fanout = 3; REG Node = 'en'
Info: Total cell delay = 2.800 ns ( 52.83 % )
Info: Total interconnect delay = 2.500 ns ( 47.17 % )
Info: - Longest clock path from clock "clk" to source register is 5.300 ns
Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 2; CLK Node = 'clk'
Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC7_A21; Fanout = 3; REG Node = 'en'
Info: Total cell delay = 2.800 ns ( 52.83 % )
Info: Total interconnect delay = 2.500 ns ( 47.17 % )
Info: + Micro clock to output delay of source is 1.100 ns
Info: + Micro setup delay of destination is 2.500 ns
Info: tco from clock "clk" to destination pin "clr" through register "en" is 16.000 ns
Info: + Longest clock path from clock "clk" to source register is 5.300 ns
Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 2; CLK Node = 'clk'
Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC7_A21; Fanout = 3; REG Node = 'en'
Info: Total cell delay = 2.800 ns ( 52.83 % )
Info: Total interconnect delay = 2.500 ns ( 47.17 % )
Info: + Micro clock to output delay of source is 1.100 ns
Info: + Longest register to pin delay is 9.600 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_A21; Fanout = 3; REG Node = 'en'
Info: 2: + IC(0.600 ns) + CELL(2.300 ns) = 2.900 ns; Loc. = LC1_A21; Fanout = 1; COMB Node = 'clr~0'
Info: 3: + IC(1.600 ns) + CELL(5.100 ns) = 9.600 ns; Loc. = PIN_143; Fanout = 0; PIN Node = 'clr'
Info: Total cell delay = 7.400 ns ( 77.08 % )
Info: Total interconnect delay = 2.200 ns ( 22.92 % )
Info: Longest tpd from source pin "clk" to destination pin "clr" is 12.900 ns
Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 2; CLK Node = 'clk'
Info: 2: + IC(1.600 ns) + CELL(1.800 ns) = 6.200 ns; Loc. = LC1_A21; Fanout = 1; COMB Node = 'clr~0'
Info: 3: + IC(1.600 ns) + CELL(5.100 ns) = 12.900 ns; Loc. = PIN_143; Fanout = 0; PIN Node = 'clr'
Info: Total cell delay = 9.700 ns ( 75.19 % )
Info: Total interconnect delay = 3.200 ns ( 24.81 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Wed Aug 10 16:32:40 2005
Info: Elapsed time: 00:00:01
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