count8.vhd

程序用VHDL实现： 利用一秒定时测量频率 并且显示

library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
entity count8 is
  port(clk:in std_logic;
       clkout:out std_logic);
end count8;

architecture rtl of count8 is
signal mid:std_logic_vector(2 downto 0);
begin 
  clkout<=mid(2);
  process(clk)
   begin
    if(clk'event and clk='1')then
          mid<=mid+1;
    end if;
  end process;
end rtl;