📄 display.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity display is
port(hou10:in std_logic_vector(3 downto 0);
hou1:in std_logic_vector(3 downto 0);
min10:in std_logic_vector(3 downto 0);
min1:in std_logic_vector(3 downto 0);
sec10:in std_logic_vector(3 downto 0);
sec1:in std_logic_vector(3 downto 0);
clk:in std_logic;
ledout:out std_logic_vector(6 downto 0);
ledpt:out std_logic;
sa,sb,sc:out std_logic);
end display;
architecture behav of display is
signal insig:integer range 0 to 12;
signal counter:integer range 0 to 5;
signal ledwk: std_logic_vector(2 downto 0);
begin
process(clk)
begin
if(clk'event and clk='1')then
if(counter=5)then
counter<=0;
else
counter<=counter+1;
end if;
end if;
end process;
process(counter,clk)
begin
if(clk'event and clk='1')then
if(counter=0)then
ledwk<="000";
insig<=conv_integer(sec1);
ledpt<='1';
elsif(counter=1)then
ledwk<="001";
insig<=conv_integer(sec10);
ledpt<='0';
elsif(counter=2)then
ledwk<="010";
insig<=conv_integer(min1);
ledpt<='1';
elsif(counter=3)then
ledwk<="011";
insig<=conv_integer(min10);
ledpt<='0';
elsif(counter=4)then
ledwk<="100";
insig<=conv_integer(hou1);
ledpt<='1';
else
ledwk<="101";
insig<=conv_integer(hou10);
ledpt<='0';
end if;
end if;
end process;
process(insig)
begin
if(insig=0)then
ledout<="0111111";
elsif(insig=1)then
ledout<="0000110";
elsif(insig=2)then
ledout<="1011011";
elsif(insig=3)then
ledout<="1001111";
elsif(insig=4)then
ledout<="1100110";
elsif(insig=5)then
ledout<="1101101";
elsif(insig=6)then
ledout<="1111101";
elsif(insig=7)then
ledout<="0000111";
elsif(insig=8)then
ledout<="1111111";
elsif(insig=9)then
ledout<="1101111";
elsif(insig=10)then
ledout<="0111000";
elsif(insig=11)then
ledout<="1000000";
elsif(insig=12)then
ledout<="0110110";
end if;
end process;
sa<=ledwk(0);
sb<=ledwk(1);
sc<=ledwk(2);
end behav;
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