frequ.map.qmsg

程序用VHDL实现： 利用一秒定时测量频率 并且显示

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Aug 10 16:32:28 2005 " "Info: Processing started: Wed Aug 10 16:32:28 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off frequ -c frequ " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off frequ -c frequ" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "display2.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file display2.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 display2-behave " "Info: Found design unit 1: display2-behave" {  } { { "display2.vhd" "" { Text "F:/EDA/plj/display2.vhd" 30 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 display2 " "Info: Found entity 1: display2" {  } { { "display2.vhd" "" { Text "F:/EDA/plj/display2.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "frequ.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file frequ.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 frequ " "Info: Found entity 1: frequ" {  } { { "frequ.bdf" "" { Schematic "F:/EDA/plj/frequ.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "display.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file display.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 display-behav " "Info: Found design unit 1: display-behav" {  } { { "display.vhd" "" { Text "F:/EDA/plj/display.vhd" 17 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 display " "Info: Found entity 1: display" {  } { { "display.vhd" "" { Text "F:/EDA/plj/display.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter10.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file counter10.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter10-rtl " "Info: Found design unit 1: counter10-rtl" {  } { { "counter10.vhd" "" { Text "F:/EDA/plj/counter10.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 counter10 " "Info: Found entity 1: counter10" {  } { { "counter10.vhd" "" { Text "F:/EDA/plj/counter10.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "control.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file control.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 control-rtl " "Info: Found design unit 1: control-rtl" {  } { { "control.vhd" "" { Text "F:/EDA/plj/control.vhd" 7 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 control " "Info: Found entity 1: control" {  } { { "control.vhd" "" { Text "F:/EDA/plj/control.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f_dis.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file f_dis.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 f_dis-rtl " "Info: Found design unit 1: f_dis-rtl" {  } { { "f_dis.vhd" "" { Text "F:/EDA/plj/f_dis.vhd" 8 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 f_dis " "Info: Found entity 1: f_dis" {  } { { "f_dis.vhd" "" { Text "F:/EDA/plj/f_dis.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "6 " "Info: Implemented 6 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "2 " "Info: Implemented 2 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "2 " "Info: Implemented 2 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Aug 10 16:32:30 2005 " "Info: Processing ended: Wed Aug 10 16:32:30 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}