📄 frequ.tan.qmsg
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register en en 125.0 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 125.0 MHz between source register \"en\" and destination register \"en\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "4.0 ns 4.0 ns 8.0 ns " "Info: fmax restricted to Clock High delay (4.0 ns) plus Clock Low delay (4.0 ns) : restricted to 8.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.800 ns + Longest register register " "Info: + Longest register to register delay is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns en 1 REG LC7_A21 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_A21; Fanout = 3; REG Node = 'en'" { } { { "F:/EDA/plj/db/frequ_cmp.qrpt" "" { Report "F:/EDA/plj/db/frequ_cmp.qrpt" Compiler "frequ" "UNKNOWN" "V1" "F:/EDA/plj/db/frequ.quartus_db" { Floorplan "F:/EDA/plj/" "" "" { en } "NODE_NAME" } "" } } { "control.vhd" "" { Text "F:/EDA/plj/control.vhd" 12 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.200 ns) 1.800 ns en 2 REG LC7_A21 3 " "Info: 2: + IC(0.600 ns) + CELL(1.200 ns) = 1.800 ns; Loc. = LC7_A21; Fanout = 3; REG Node = 'en'" { } { { "F:/EDA/plj/db/frequ_cmp.qrpt" "" { Report "F:/EDA/plj/db/frequ_cmp.qrpt" Compiler "frequ" "UNKNOWN" "V1" "F:/EDA/plj/db/frequ.quartus_db" { Floorplan "F:/EDA/plj/" "" "1.800 ns" { en en } "NODE_NAME" } "" } } { "control.vhd" "" { Text "F:/EDA/plj/control.vhd" 12 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.200 ns 66.67 % " "Info: Total cell delay = 1.200 ns ( 66.67 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns 33.33 % " "Info: Total interconnect delay = 0.600 ns ( 33.33 % )" { } { } 0} } { { "F:/EDA/plj/db/frequ_cmp.qrpt" "" { Report "F:/EDA/plj/db/frequ_cmp.qrpt" Compiler "frequ" "UNKNOWN" "V1" "F:/EDA/plj/db/frequ.quartus_db" { Floorplan "F:/EDA/plj/" "" "1.800 ns" { en en } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { en en } { 0.000ns 0.600ns } { 0.000ns 1.200ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.300 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_55 2 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 2; CLK Node = 'clk'" { } { { "F:/EDA/plj/db/frequ_cmp.qrpt" "" { Report "F:/EDA/plj/db/frequ_cmp.qrpt" Compiler "frequ" "UNKNOWN" "V1" "F:/EDA/plj/db/frequ.quartus_db" { Floorplan "F:/EDA/plj/" "" "" { clk } "NODE_NAME" } "" } } { "control.vhd" "" { Text "F:/EDA/plj/control.vhd" 4 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns en 2 REG LC7_A21 3 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC7_A21; Fanout = 3; REG Node = 'en'" { } { { "F:/EDA/plj/db/frequ_cmp.qrpt" "" { Report "F:/EDA/plj/db/frequ_cmp.qrpt" Compiler "frequ" "UNKNOWN" "V1" "F:/EDA/plj/db/frequ.quartus_db" { Floorplan "F:/EDA/plj/" "" "2.500 ns" { clk en } "NODE_NAME" } "" } } { "control.vhd" "" { Text "F:/EDA/plj/control.vhd" 12 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" { } { } 0} } { { "F:/EDA/plj/db/frequ_cmp.qrpt" "" { Report "F:/EDA/plj/db/frequ_cmp.qrpt" Compiler "frequ" "UNKNOWN" "V1" "F:/EDA/plj/db/frequ.quartus_db" { Floorplan "F:/EDA/plj/" "" "5.300 ns" { clk en } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out en } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.300 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_55 2 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 2; CLK Node = 'clk'" { } { { "F:/EDA/plj/db/frequ_cmp.qrpt" "" { Report "F:/EDA/plj/db/frequ_cmp.qrpt" Compiler "frequ" "UNKNOWN" "V1" "F:/EDA/plj/db/frequ.quartus_db" { Floorplan "F:/EDA/plj/" "" "" { clk } "NODE_NAME" } "" } } { "control.vhd" "" { Text "F:/EDA/plj/control.vhd" 4 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns en 2 REG LC7_A21 3 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC7_A21; Fanout = 3; REG Node = 'en'" { } { { "F:/EDA/plj/db/frequ_cmp.qrpt" "" { Report "F:/EDA/plj/db/frequ_cmp.qrpt" Compiler "frequ" "UNKNOWN" "V1" "F:/EDA/plj/db/frequ.quartus_db" { Floorplan "F:/EDA/plj/" "" "2.500 ns" { clk en } "NODE_NAME" } "" } } { "control.vhd" "" { Text "F:/EDA/plj/control.vhd" 12 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" { } { } 0} } { { "F:/EDA/plj/db/frequ_cmp.qrpt" "" { Report "F:/EDA/plj/db/frequ_cmp.qrpt" Compiler "frequ" "UNKNOWN" "V1" "F:/EDA/plj/db/frequ.quartus_db" { Floorplan "F:/EDA/plj/" "" "5.300 ns" { clk en } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out en } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } } 0} } { { "F:/EDA/plj/db/frequ_cmp.qrpt" "" { Report "F:/EDA/plj/db/frequ_cmp.qrpt" Compiler "frequ" "UNKNOWN" "V1" "F:/EDA/plj/db/frequ.quartus_db" { Floorplan "F:/EDA/plj/" "" "5.300 ns" { clk en } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out en } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "F:/EDA/plj/db/frequ_cmp.qrpt" "" { Report "F:/EDA/plj/db/frequ_cmp.qrpt" Compiler "frequ" "UNKNOWN" "V1" "F:/EDA/plj/db/frequ.quartus_db" { Floorplan "F:/EDA/plj/" "" "5.300 ns" { clk en } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out en } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" { } { { "control.vhd" "" { Text "F:/EDA/plj/control.vhd" 12 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" { } { { "control.vhd" "" { Text "F:/EDA/plj/control.vhd" 12 -1 0 } } } 0} } { { "F:/EDA/plj/db/frequ_cmp.qrpt" "" { Report "F:/EDA/plj/db/frequ_cmp.qrpt" Compiler "frequ" "UNKNOWN" "V1" "F:/EDA/plj/db/frequ.quartus_db" { Floorplan "F:/EDA/plj/" "" "1.800 ns" { en en } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { en en } { 0.000ns 0.600ns } { 0.000ns 1.200ns } } } { "F:/EDA/plj/db/frequ_cmp.qrpt" "" { Report "F:/EDA/plj/db/frequ_cmp.qrpt" Compiler "frequ" "UNKNOWN" "V1" "F:/EDA/plj/db/frequ.quartus_db" { Floorplan "F:/EDA/plj/" "" "5.300 ns" { clk en } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out en } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "F:/EDA/plj/db/frequ_cmp.qrpt" "" { Report "F:/EDA/plj/db/frequ_cmp.qrpt" Compiler "frequ" "UNKNOWN" "V1" "F:/EDA/plj/db/frequ.quartus_db" { Floorplan "F:/EDA/plj/" "" "5.300 ns" { clk en } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out en } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } } 0} } { { "F:/EDA/plj/db/frequ_cmp.qrpt" "" { Report "F:/EDA/plj/db/frequ_cmp.qrpt" Compiler "frequ" "UNKNOWN" "V1" "F:/EDA/plj/db/frequ.quartus_db" { Floorplan "F:/EDA/plj/" "" "" { en } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { en } { } { } } } { "control.vhd" "" { Text "F:/EDA/plj/control.vhd" 12 -1 0 } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk clr en 16.000 ns register " "Info: tco from clock \"clk\" to destination pin \"clr\" through register \"en\" is 16.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.300 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_55 2 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 2; CLK Node = 'clk'" { } { { "F:/EDA/plj/db/frequ_cmp.qrpt" "" { Report "F:/EDA/plj/db/frequ_cmp.qrpt" Compiler "frequ" "UNKNOWN" "V1" "F:/EDA/plj/db/frequ.quartus_db" { Floorplan "F:/EDA/plj/" "" "" { clk } "NODE_NAME" } "" } } { "control.vhd" "" { Text "F:/EDA/plj/control.vhd" 4 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns en 2 REG LC7_A21 3 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC7_A21; Fanout = 3; REG Node = 'en'" { } { { "F:/EDA/plj/db/frequ_cmp.qrpt" "" { Report "F:/EDA/plj/db/frequ_cmp.qrpt" Compiler "frequ" "UNKNOWN" "V1" "F:/EDA/plj/db/frequ.quartus_db" { Floorplan "F:/EDA/plj/" "" "2.500 ns" { clk en } "NODE_NAME" } "" } } { "control.vhd" "" { Text "F:/EDA/plj/control.vhd" 12 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" { } { } 0} } { { "F:/EDA/plj/db/frequ_cmp.qrpt" "" { Report "F:/EDA/plj/db/frequ_cmp.qrpt" Compiler "frequ" "UNKNOWN" "V1" "F:/EDA/plj/db/frequ.quartus_db" { Floorplan "F:/EDA/plj/" "" "5.300 ns" { clk en } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out en } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" { } { { "control.vhd" "" { Text "F:/EDA/plj/control.vhd" 12 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.600 ns + Longest register pin " "Info: + Longest register to pin delay is 9.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns en 1 REG LC7_A21 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_A21; Fanout = 3; REG Node = 'en'" { } { { "F:/EDA/plj/db/frequ_cmp.qrpt" "" { Report "F:/EDA/plj/db/frequ_cmp.qrpt" Compiler "frequ" "UNKNOWN" "V1" "F:/EDA/plj/db/frequ.quartus_db" { Floorplan "F:/EDA/plj/" "" "" { en } "NODE_NAME" } "" } } { "control.vhd" "" { Text "F:/EDA/plj/control.vhd" 12 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 2.900 ns clr~0 2 COMB LC1_A21 1 " "Info: 2: + IC(0.600 ns) + CELL(2.300 ns) = 2.900 ns; Loc. = LC1_A21; Fanout = 1; COMB Node = 'clr~0'" { } { { "F:/EDA/plj/db/frequ_cmp.qrpt" "" { Report "F:/EDA/plj/db/frequ_cmp.qrpt" Compiler "frequ" "UNKNOWN" "V1" "F:/EDA/plj/db/frequ.quartus_db" { Floorplan "F:/EDA/plj/" "" "2.900 ns" { en clr~0 } "NODE_NAME" } "" } } { "control.vhd" "" { Text "F:/EDA/plj/control.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(5.100 ns) 9.600 ns clr 3 PIN PIN_143 0 " "Info: 3: + IC(1.600 ns) + CELL(5.100 ns) = 9.600 ns; Loc. = PIN_143; Fanout = 0; PIN Node = 'clr'" { } { { "F:/EDA/plj/db/frequ_cmp.qrpt" "" { Report "F:/EDA/plj/db/frequ_cmp.qrpt" Compiler "frequ" "UNKNOWN" "V1" "F:/EDA/plj/db/frequ.quartus_db" { Floorplan "F:/EDA/plj/" "" "6.700 ns" { clr~0 clr } "NODE_NAME" } "" } } { "control.vhd" "" { Text "F:/EDA/plj/control.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.400 ns 77.08 % " "Info: Total cell delay = 7.400 ns ( 77.08 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.200 ns 22.92 % " "Info: Total interconnect delay = 2.200 ns ( 22.92 % )" { } { } 0} } { { "F:/EDA/plj/db/frequ_cmp.qrpt" "" { Report "F:/EDA/plj/db/frequ_cmp.qrpt" Compiler "frequ" "UNKNOWN" "V1" "F:/EDA/plj/db/frequ.quartus_db" { Floorplan "F:/EDA/plj/" "" "9.600 ns" { en clr~0 clr } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "9.600 ns" { en clr~0 clr } { 0.000ns 0.600ns 1.600ns } { 0.000ns 2.300ns 5.100ns } } } } 0} } { { "F:/EDA/plj/db/frequ_cmp.qrpt" "" { Report "F:/EDA/plj/db/frequ_cmp.qrpt" Compiler "frequ" "UNKNOWN" "V1" "F:/EDA/plj/db/frequ.quartus_db" { Floorplan "F:/EDA/plj/" "" "5.300 ns" { clk en } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out en } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "F:/EDA/plj/db/frequ_cmp.qrpt" "" { Report "F:/EDA/plj/db/frequ_cmp.qrpt" Compiler "frequ" "UNKNOWN" "V1" "F:/EDA/plj/db/frequ.quartus_db" { Floorplan "F:/EDA/plj/" "" "9.600 ns" { en clr~0 clr } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "9.600 ns" { en clr~0 clr } { 0.000ns 0.600ns 1.600ns } { 0.000ns 2.300ns 5.100ns } } } } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "clk clr 12.900 ns Longest " "Info: Longest tpd from source pin \"clk\" to destination pin \"clr\" is 12.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_55 2 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 2; CLK Node = 'clk'" { } { { "F:/EDA/plj/db/frequ_cmp.qrpt" "" { Report "F:/EDA/plj/db/frequ_cmp.qrpt" Compiler "frequ" "UNKNOWN" "V1" "F:/EDA/plj/db/frequ.quartus_db" { Floorplan "F:/EDA/plj/" "" "" { clk } "NODE_NAME" } "" } } { "control.vhd" "" { Text "F:/EDA/plj/control.vhd" 4 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.800 ns) 6.200 ns clr~0 2 COMB LC1_A21 1 " "Info: 2: + IC(1.600 ns) + CELL(1.800 ns) = 6.200 ns; Loc. = LC1_A21; Fanout = 1; COMB Node = 'clr~0'" { } { { "F:/EDA/plj/db/frequ_cmp.qrpt" "" { Report "F:/EDA/plj/db/frequ_cmp.qrpt" Compiler "frequ" "UNKNOWN" "V1" "F:/EDA/plj/db/frequ.quartus_db" { Floorplan "F:/EDA/plj/" "" "3.400 ns" { clk clr~0 } "NODE_NAME" } "" } } { "control.vhd" "" { Text "F:/EDA/plj/control.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(5.100 ns) 12.900 ns clr 3 PIN PIN_143 0 " "Info: 3: + IC(1.600 ns) + CELL(5.100 ns) = 12.900 ns; Loc. = PIN_143; Fanout = 0; PIN Node = 'clr'" { } { { "F:/EDA/plj/db/frequ_cmp.qrpt" "" { Report "F:/EDA/plj/db/frequ_cmp.qrpt" Compiler "frequ" "UNKNOWN" "V1" "F:/EDA/plj/db/frequ.quartus_db" { Floorplan "F:/EDA/plj/" "" "6.700 ns" { clr~0 clr } "NODE_NAME" } "" } } { "control.vhd" "" { Text "F:/EDA/plj/control.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.700 ns 75.19 % " "Info: Total cell delay = 9.700 ns ( 75.19 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.200 ns 24.81 % " "Info: Total interconnect delay = 3.200 ns ( 24.81 % )" { } { } 0} } { { "F:/EDA/plj/db/frequ_cmp.qrpt" "" { Report "F:/EDA/plj/db/frequ_cmp.qrpt" Compiler "frequ" "UNKNOWN" "V1" "F:/EDA/plj/db/frequ.quartus_db" { Floorplan "F:/EDA/plj/" "" "12.900 ns" { clk clr~0 clr } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "12.900 ns" { clk clk~out clr~0 clr } { 0.000ns 0.000ns 1.600ns 1.600ns } { 0.000ns 2.800ns 1.800ns 5.100ns } } } } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Aug 10 16:32:40 2005 " "Info: Processing ended: Wed Aug 10 16:32:40 2005" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0} } { } 0}
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