counter10.vhd

来自「程序用VHDL实现： 利用一秒定时测量频率 并且显示」· VHDL 代码 · 共 36 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter10 is
port(clr,en,clk:in std_logic;
     carry0:out std_logic;
     q:out std_logic_vector(3 downto 0));
end ;
architecture rtl of counter10 is
   signal qs:std_logic_vector(3 downto 0);   

 begin
     process(clk,clr)        
        begin
         if clr='0' then
             qs<="0000";
         elsif(clk'event and clk='1') then
            if en='1' then  
              if qs<9 then         
              qs<=qs+1;
              else
              qs<="0000";                          
             end if;
            end if;
          end if;
     end process;
     process(qs)
        begin 
           if qs=9 then
               carry0<='1';
            else
               carry0<='0';
           end if;
     end process;
  q<=qs;
end rtl;