f_dis.vhd

程序用VHDL实现： 利用一秒定时测量频率 并且显示

library ieee;
use ieee.std_logic_1164.all;
entity f_dis is
   port (en :in std_logic;
           q:in std_logic_vector(3 downto 0);
           y:out std_logic_vector(3 downto 0));
end ;
architecture rtl of f_dis is
signal indata :std_logic_vector(3 downto 0);
begin 
    process(en)
    begin
      if  en='0' then--en＝0时锁存
        indata<=q;     
      end if;
     end process;
   y<=indata;
end rtl;