control.vhd

来自「程序用VHDL实现： 利用一秒定时测量频率 并且显示」· VHDL 代码 · 共 24 行

library ieee;
use ieee.std_logic_1164.all;
entity  control is
    port (clk ,start:in std_logic;
          cnt_en,clr:out std_logic);
end;
architecture rtl of control is
signal en:std_logic;
begin 
   process(clk,start)  
     begin 
        if start='0' then        
           en<='0';
         elsif (clk'event and clk='1')then
           en<=not en;                             
        end if ;             
    end process;
    process(clk,en)
    begin
      clr<= not(not(en) and  not(clk)); 
    end process; 
    cnt_en<=en;  
end rtl;