frequ.fit.eqn

程序用VHDL实现： 利用一秒定时测量频率 并且显示

--en is en at LC7_A21
--operation mode is normal

en_lut_out = !en;
en = DFFEA(en_lut_out, GLOBAL(clk), GLOBAL(start), , , , );


--A1L3 is clr~0 at LC1_A21
--operation mode is normal

A1L3 = en # clk;


--clk is clk at PIN_55
--operation mode is input

clk = INPUT();


--start is start at PIN_126
--operation mode is input

start = INPUT();


--cnt_en is cnt_en at PIN_7
--operation mode is output

cnt_en = OUTPUT(en);


--clr is clr at PIN_143
--operation mode is output

clr = OUTPUT(A1L3);