count24.vhd

程序用VHDL实现： 利用一秒定时测量频率 并且显示

library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
entity count24 is
  port(clk:in std_logic;
       bcd1:out std_logic_vector(3 downto 0);
       bcd10p:out std_logic_vector(1 downto 0));
end count24;
architecture rtl of count24 is
signal bcd1n:std_logic_vector(4 downto 0);
signal bcd10n:std_logic_vector(1 downto 0);
signal count:std_logic_vector(4 downto 0);
begin 
   bcd1<=bcd1n(3 downto 0);
   bcd10p<=bcd10n;
   process(clk)
     begin
        if(clk'event and clk='1')then
         if(count=23)then
          count<="00000";
         else
          count<=count+1;
         end if;
       end if;
    end process;
process(clk)
 begin
  if(clk'event and clk='1')then
    if(count>=20)then
     bcd10n<="10";
     bcd1n<=count-20;
    elsif(count>=10)then
     bcd10n<="01";
     bcd1n<=count-10;
    else
     bcd10n<="00";
     bcd1n<=count;
    end if;
  end if;
end process;
end rtl;