mux2.vhd

来自「程序用VHDL实现： 利用一秒定时测量频率 并且显示」· VHDL 代码 · 共 17 行

library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
entity mux2 is
  port(in0,in1,sel:in std_logic;
       y:out std_logic);
end mux2;

architecture rtl of mux2 is
signal temp1,temp2,temp3:std_logic;
begin 
   temp1<=in0 and sel;
   temp2<=in1 and (not sel);
   temp3<=temp1 or temp2;
   y<=temp3; 
   end rtl;