step_motor.vho

步进电机控制器,控制电机的VHDL源程序

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic       
-- functions, and any output files any of the foregoing           
-- (including device programming or simulation files), and any    
-- associated documentation or information are expressly subject  
-- to the terms and conditions of the Altera Program License      
-- Subscription Agreement, Altera MegaCore Function License       
-- Agreement, or other applicable license agreement, including,   
-- without limitation, that your use is for the sole purpose of   
-- programming logic devices manufactured by Altera and sold by   
-- Altera or its authorized distributors.  Please refer to the    
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version"

-- DATE "08/13/2005 13:16:20"

-- 
-- Device: Altera EPM7128SLC84-15 Package PLCC84
-- 

-- 
-- This VHDL file should be used for PRIMETIME only
-- 

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY 	step_motor IS
    PORT (
	f : IN std_logic;
	p : IN std_logic;
	d : IN std_logic;
	speed : IN std_logic_vector(1 DOWNTO 0);
	coil : OUT std_logic_vector(3 DOWNTO 0)
	);
END step_motor;

ARCHITECTURE structure OF step_motor IS
SIGNAL GNDs : std_logic_vector(255 DOWNTO 0);
SIGNAL VCCs : std_logic_vector(255 DOWNTO 0);
SIGNAL gnd : std_logic;
SIGNAL vcc : std_logic;
SIGNAL lcell_ff_enable_asynch_arcs_out : std_logic;
SIGNAL ww_f : std_logic;
SIGNAL ww_p : std_logic;
SIGNAL ww_d : std_logic;
SIGNAL ww_speed : std_logic_vector(1 DOWNTO 0);
SIGNAL ww_coil : std_logic_vector(3 DOWNTO 0);
SIGNAL B_aI_pterm0_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL B_aI_pterm1_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL B_aI_pterm2_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL B_aI_pterm3_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL B_aI_pterm4_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL B_aI_pterm5_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL B_aI_pxor_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL B_aI_pclk_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL B_aI_pena_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL B_aI_paclr_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL B_aI_papre_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL a_aprocess4_aB_aI_pterm0_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL a_aprocess4_aB_aI_pterm1_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL a_aprocess4_aB_aI_pterm2_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL a_aprocess4_aB_aI_pterm3_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL a_aprocess4_aB_aI_pterm4_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL a_aprocess4_aB_aI_pterm5_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL a_aprocess4_aB_aI_pxor_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL a_aprocess4_aB_aI_pclk_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL a_aprocess4_aB_aI_pena_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL a_aprocess4_aB_aI_paclr_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL a_aprocess4_aB_aI_papre_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a839_I_pterm0_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a839_I_pterm1_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a839_I_pterm2_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a839_I_pterm3_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a839_I_pterm4_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a839_I_pterm5_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a839_I_pxor_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a839_I_pclk_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a839_I_pena_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a839_I_paclr_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a839_I_papre_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a845_I_pterm0_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a845_I_pterm1_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a845_I_pterm2_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a845_I_pterm3_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a845_I_pterm4_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a845_I_pterm5_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a845_I_pxor_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a845_I_pclk_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a845_I_pena_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a845_I_paclr_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a845_I_papre_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a851_I_pterm0_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a851_I_pterm1_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a851_I_pterm2_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a851_I_pterm3_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a851_I_pterm4_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a851_I_pterm5_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a851_I_pxor_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a851_I_pclk_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a851_I_pena_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a851_I_paclr_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a851_I_papre_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a857_I_pterm0_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a857_I_pterm1_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a857_I_pterm2_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a857_I_pterm3_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a857_I_pterm4_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a857_I_pterm5_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a857_I_pxor_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a857_I_pclk_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a857_I_pena_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a857_I_paclr_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a857_I_papre_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a863_I_pterm0_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a863_I_pterm1_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a863_I_pterm2_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a863_I_pterm3_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a863_I_pterm4_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a863_I_pterm5_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a863_I_pxor_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a863_I_pclk_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a863_I_pena_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a863_I_paclr_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a863_I_papre_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a877_I_pterm0_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a877_I_pterm1_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a877_I_pterm2_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a877_I_pterm3_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a877_I_pterm4_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a877_I_pterm5_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a877_I_pxor_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a877_I_pclk_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a877_I_pena_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a877_I_paclr_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a877_I_papre_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a878_I_pterm0_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a878_I_pterm1_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a878_I_pterm2_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a878_I_pterm3_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a878_I_pterm4_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a878_I_pterm5_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a878_I_pxor_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a878_I_pclk_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a878_I_pena_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a878_I_paclr_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL LessThan_a878_I_papre_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL d_ff_rtl_0_adffs_a0_a_aI_pterm0_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL d_ff_rtl_0_adffs_a0_a_aI_pterm1_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL d_ff_rtl_0_adffs_a0_a_aI_pterm2_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL d_ff_rtl_0_adffs_a0_a_aI_pterm3_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL d_ff_rtl_0_adffs_a0_a_aI_pterm4_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL d_ff_rtl_0_adffs_a0_a_aI_pterm5_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL d_ff_rtl_0_adffs_a0_a_aI_pxor_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL d_ff_rtl_0_adffs_a0_a_aI_pclk_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL d_ff_rtl_0_adffs_a0_a_aI_pena_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL d_ff_rtl_0_adffs_a0_a_aI_paclr_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL d_ff_rtl_0_adffs_a0_a_aI_papre_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL delay_rtl_1_adffs_a0_a_aI_pterm0_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL delay_rtl_1_adffs_a0_a_aI_pterm1_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL delay_rtl_1_adffs_a0_a_aI_pterm2_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL delay_rtl_1_adffs_a0_a_aI_pterm3_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL delay_rtl_1_adffs_a0_a_aI_pterm4_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL delay_rtl_1_adffs_a0_a_aI_pterm5_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL delay_rtl_1_adffs_a0_a_aI_pxor_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL delay_rtl_1_adffs_a0_a_aI_pclk_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL delay_rtl_1_adffs_a0_a_aI_pena_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL delay_rtl_1_adffs_a0_a_aI_paclr_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL delay_rtl_1_adffs_a0_a_aI_papre_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL PHASE_aI_pterm0_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL PHASE_aI_pterm1_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL PHASE_aI_pterm2_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL PHASE_aI_pterm3_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL PHASE_aI_pterm4_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL PHASE_aI_pterm5_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL PHASE_aI_pxor_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL PHASE_aI_pclk_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL PHASE_aI_pena_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL PHASE_aI_paclr_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL PHASE_aI_papre_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL DIRECTION_aI_pterm0_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL DIRECTION_aI_pterm1_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL DIRECTION_aI_pterm2_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL DIRECTION_aI_pterm3_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL DIRECTION_aI_pterm4_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL DIRECTION_aI_pterm5_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL DIRECTION_aI_pxor_bus : std_logic_vector(51 DOWNTO 0);