controll.vhd

具有多种功能的电子钟：闹钟

library ieee;                    --顶层
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity controll is
  port(clk:in std_logic;                  
	   keya:in std_logic;           --a确认
       keyb:in std_logic;           --b取消      
       keyc:in std_logic;           --c报时开关;
       keyd:in std_logic;           -- d闹钟开关   
       keye:in std_logic;           --e设置时间
       keyf:in std_logic;           --f设置闹钟 
       keyg:in std_logic;           -- g数值增加
       displaytime: out std_logic_vector(23 downto 0); --显示时间
       sound_signal:out std_logic);                     --蜂鸣器驱动
   
end controll;
 architecture con of controll is
component condition 
 port (clk:in std_logic;
	   keya,keyb,keye,keyf,keyg:in std_logic;  --a确认；b取消；c报时开关;
													  -- d闹钟开关；e设置时间；f设置闹钟；
                                                      -- g数值增加
       buffertime: buffer std_logic_vector(23 downto 0); --缓存时间
       iscount:out std_logic;                           --计数
       alarmload:out std_logic;                         --闹钟
	   timeload: out std_logic);                       --设置时间
end component;

component counter 
port(  clk: in std_logic;
 	   rst: in std_logic;  --计数使能
	   buffertime: in std_logic_vector(23 downto 0 ); --时间加载
	   time: out std_logic_vector(23 downto 0));
end component;

component statemachine 
	port(clk: in std_logic;
		 keyc,keyd: in std_logic;  --c报时开关；d闹钟开关；
         alarmon: out std_logic;    --闹钟信号 
		 houralarmon :out std_logic);  --计数时间信号
end component;

component alarmreg is
 port(clk:in std_logic;
	  alarmload:in std_logic;                       --闹钟信号
	  buffertime:in std_logic_vector(23 downto 0);  --时间数据
 	  alarmtime: out std_logic_vector(23 downto 0));--寄存器输出
 end component;

component sound is
  port(alarmtime: in std_logic_vector(23 downto 0);  --闹钟预定时间
       clk: in std_logic;
       time:in std_logic_vector(23 downto 0);        --当前时间
	   alarmon :in std_logic;                        --闹钟开关
       houralarmon: in std_logic;                    --报时开关
       sound_signal: out std_logic);                 --闹钟信号
end component;

signal buffertime :std_logic_vector(23 downto 0);
signal timeload: std_logic;
signal iscount:std_logic;
signal alarmload :std_logic;
signal alarmon:std_logic;
signal houralarmon:std_logic;
--当前时间
signal time :std_logic_vector(23 downto 0);
--闹钟时间
signal alarmtime:std_logic_vector(23 downto 0);

begin
	u1:condition
		port map(clk,keya,keyb,keye,keyf,keyg,buffertime,iscount,
                  alarmload,timeload);
    u2:counter
        port map(clk,timeload,buffertime,time);
    
    u3:statemachine
        port map(clk,keyc,keyd,alarmon,houralarmon);
    
    u4:alarmreg
        port map(clk,alarmload,buffertime,alarmtime);
    
	u5:sound
		port map(alarmtime,clk,time,alarmon,houralarmon,sound_signal);
    
  --多路选通器
    process(iscount,time,buffertime)
		begin
			if(iscount='1')then
               displaytime<=time;
			else 
			   displaytime<=buffertime;
          end if;
  end process;
end con;