led.vhd

来自「具有多种功能的电子钟：闹钟」· VHDL 代码 · 共 47 行

library ieee;                    --综合
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity led is
  port(clk:in std_logic;
	   keya:in std_logic;           --a确认
       keyb:in std_logic;           --b取消      
       keyc:in std_logic;           --c报时开关;
       keyd:in std_logic;           -- d闹钟开关   
       keye:in std_logic;           --e设置时间
       keyf:in std_logic;           --f设置闹钟 
       keyg:in std_logic;           -- g数值增加
       sound_signal:out std_logic;                     --蜂鸣器驱动
       led_s:out std_logic_vector(2 downto 0);
       ledout:out std_logic_vector(6 downto 0));
end led;
architecture ff of led is
component controll
   port(clk:in std_logic;                  
	   keya:in std_logic;           --a确认
       keyb:in std_logic;           --b取消      
       keyc:in std_logic;           --c报时开关;
       keyd:in std_logic;           -- d闹钟开关   
       keye:in std_logic;           --e设置时间
       keyf:in std_logic;           --f设置闹钟 
       keyg:in std_logic;           -- g数值增加
       displaytime: out std_logic_vector(23 downto 0); --显示时间
       sound_signal:out std_logic);                     --蜂鸣器驱动
   end component;

component display
  port (clk:in std_logic;
	   displaytime: in std_logic_vector(23 downto 0);
       led_s:out std_logic_vector(2 downto 0);
      ledout:out std_logic_vector(6 downto 0));
end component;

signal displaytime:std_logic_vector(23 downto 0);
begin
  u1:controll
      port map(clk,keya,keyb,keyc,keyd,keye,keyf,keyg,displaytime,sound_signal);
 u2: display
  port map(clk,displaytime,led_s,ledout);
end ff;