oc8051_decoder.v

8051的Verilog

          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_DES;
          
        end
      `OC8051_CJNE_R : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel2 = `OC8051_ASS_IMM;
          alu_op = `OC8051_ALU_PCS;
          wr = 1'b0;
          psw_set = `OC8051_PS_NOT;
          cy_sel = `OC8051_CY_0;
          pc_wr = `OC8051_PCW_N;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP3_PCL;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          
        end
      `OC8051_CJNE_I : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel2 = `OC8051_ASS_IMM;
          alu_op = `OC8051_ALU_PCS;
          wr = 1'b0;
          psw_set = `OC8051_PS_NOT;
          cy_sel = `OC8051_CY_0;
          pc_wr = `OC8051_PCW_N;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP3_PCL;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          
        end
      `OC8051_CJNE_D : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel2 = `OC8051_ASS_IMM;
          alu_op = `OC8051_ALU_PCS;
          wr = 1'b0;
          psw_set = `OC8051_PS_NOT;
          cy_sel = `OC8051_CY_0;
          pc_wr = `OC8051_PCW_N;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP3_PCL;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          
        end
      `OC8051_CJNE_C : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel2 = `OC8051_ASS_IMM;
          alu_op = `OC8051_ALU_PCS;
          wr = 1'b0;
          psw_set = `OC8051_PS_NOT;
          cy_sel = `OC8051_CY_0;
          pc_wr = `OC8051_PCW_N;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP3_PCL;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          
        end
      `OC8051_DJNZ_R : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel2 = `OC8051_ASS_IMM;
          alu_op = `OC8051_ALU_PCS;
          wr = 1'b0;
          psw_set = `OC8051_PS_NOT;
          cy_sel = `OC8051_CY_0;
          pc_wr = `OC8051_PCW_N;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP2_PCL;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          
        end
      `OC8051_DJNZ_D : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel2 = `OC8051_ASS_IMM;
          alu_op = `OC8051_ALU_PCS;
          wr = 1'b0;
          psw_set = `OC8051_PS_NOT;
          cy_sel = `OC8051_CY_0;
          pc_wr = `OC8051_PCW_N;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP3_PCL;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          
        end
      `OC8051_RET : begin
          ram_rd_sel = `OC8051_RRS_SP;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel2 = `OC8051_ASS_DC;
          alu_op = `OC8051_ALU_NOP;
          wr = 1'b0;
          psw_set = `OC8051_PS_NOT;
          cy_sel = `OC8051_CY_0;
          pc_wr = `OC8051_PCW_Y;
          pc_sel = `OC8051_PIS_SP;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          
        end
      `OC8051_RETI : begin
          ram_rd_sel = `OC8051_RRS_SP;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel2 = `OC8051_ASS_DC;
          alu_op = `OC8051_ALU_NOP;
          wr = 1'b0;
          psw_set = `OC8051_PS_NOT;
          cy_sel = `OC8051_CY_0;
          pc_wr = `OC8051_PCW_Y;
          pc_sel = `OC8051_PIS_SP;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          
        end
      `OC8051_DIV : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_B;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel2 = `OC8051_ASS_RAM;
          alu_op = `OC8051_ALU_DIV;
          wr = 1'b0;
          psw_set = `OC8051_PS_OV;
          cy_sel = `OC8051_CY_0;
          pc_wr = `OC8051_PCW_N;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          
        end
      `OC8051_MUL : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_B;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel2 = `OC8051_ASS_RAM;
          alu_op = `OC8051_ALU_MUL;
          wr = 1'b0;
          psw_set = `OC8051_PS_OV;
          cy_sel = `OC8051_CY_0;
          pc_wr = `OC8051_PCW_N;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          
        end
     default begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_DC;
          src_sel2 = `OC8051_ASS_DC;
          alu_op = `OC8051_ALU_NOP;
          wr = 1'b0;
          psw_set = `OC8051_PS_NOT;
          cy_sel = `OC8051_CY_0;
          pc_wr = `OC8051_PCW_N;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          
      end
    endcase
    default: begin
    casex (op_cur)
      `OC8051_ACALL :begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_SP;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel2 = `OC8051_ASS_DC;
          alu_op = `OC8051_ALU_NOP;
          imm_sel = `OC8051_IDS_PCL;
          wr = 1'b1;
          psw_set = `OC8051_PS_NOT;
          cy_sel = `OC8051_CY_0;
          pc_wr = `OC8051_PCW_Y;
          pc_sel = `OC8051_PIS_I11;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          stb_i = 1'b0;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          
        end
      `OC8051_AJMP : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_DC;
          src_sel2 = `OC8051_ASS_DC;
          alu_op = `OC8051_ALU_NOP;
          imm_sel = `OC8051_IDS_DC;
          wr = 1'b0;
          psw_set = `OC8051_PS_NOT;
          cy_sel = `OC8051_CY_0;
          pc_wr = `OC8051_PCW_Y;
          pc_sel = `OC8051_PIS_I11;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          stb_i = 1'b0;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          
        end
      `OC8051_ADD_R : begin
	  ram_rd_sel = `OC8051_RRS_RN;
	  ram_wr_sel = `OC8051_RWS_ACC;
	  src_sel1 = `OC8051_ASS_ACC;
	  src_sel2 = `OC8051_ASS_RAM;
	  alu_op = `OC8051_ALU_ADD;
          wr = 1'b1;
	  psw_set = `OC8051_PS_AC;
	  cy_sel = `OC8051_CY_0;
          pc_wr = `OC8051_PCW_N;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          
        end
      `OC8051_ADDC_R : begin
	  ram_rd_sel = `OC8051_RRS_RN;
	  ram_wr_sel = `OC8051_RWS_ACC;
	  src_sel1 = `OC8051_ASS_ACC;
	  src_sel2 = `OC8051_ASS_RAM;
	  alu_op = `OC8051_ALU_ADD;
          wr = 1'b1;
	  psw_set = `OC8051_PS_AC;
	  cy_sel = `OC8051_CY_PSW;
          pc_wr = `OC8051_PCW_N;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          
        end
      `OC8051_ANL_R : begin
          ram_rd_sel = `OC8051_RRS_RN;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel2 = `OC8051_ASS_RAM;
          alu_op = `OC8051_ALU_AND;
          wr = 1'b1;
          psw_set = `OC8051_PS_NOT;
          cy_sel = `OC8051_CY_0;
          pc_wr = `OC8051_PCW_N;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          
        end
      `OC8051_CJNE_R : begin
          ram_rd_sel = `OC8051_RRS_RN;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel2 = `OC8051_ASS_IMM;
          alu_op = `OC8051_ALU_SUB;
          wr = 1'b0;
          psw_set = `OC8051_PS_CY;
          cy_sel = `OC8051_CY_0;
          pc_wr = `OC8051_PCW_N;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP2;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          stb_i = 1'b0;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          
        end
      `OC8051_DEC_R : begin
          ram_rd_sel = `OC8051_RRS_RN;
          ram_wr_sel = `OC8051_RWS_RN;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel2 = `OC8051_ASS_ZERO;
          alu_op = `OC8051_ALU_SUB;
          wr = 1'b1;
          psw_set = `OC8051_PS_NOT;
          cy_sel = `OC8051_CY_1;
          pc_wr = `OC8051_PCW_N;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
          stb_i = 1'b1;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          
        end
      `OC8051_DJNZ_R : begin
          ram_rd_sel = `OC8051_RRS_RN;
          ram_wr_sel = `OC8051_RWS_RN;
          src_sel1 = `OC8051_ASS_RAM;
          src_sel2 = `OC8051_ASS_ZERO;
          alu_op = `OC8051_ALU_SUB;
          wr = 1'b1;
          psw_set = `OC8051_PS_NOT;
          cy_sel = `OC8051_CY_1;
          pc_wr = `OC8051_PCW_N;
          pc_sel = `OC8051_PIS_DC;