oc8051_decoder.v

来自「8051的Verilog」· Verilog 代码 · 共 1,896 行 · 第 1/5 页

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          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DES;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          stb_i = 1'b1;          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          
          
        end
      `OC8051_DJNZ_R : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_DC;
          src_sel2 = `OC8051_ASS_DC;
          alu_op = `OC8051_ALU_NOP;
          wr = 1'b0;
          psw_set = `OC8051_PS_NOT;
          cy_sel = `OC8051_CY_0;
          pc_wr = !eq;
          pc_sel = `OC8051_PIS_ALU;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DES;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          stb_i = 1'b1;          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          

        end
      `OC8051_DJNZ_D : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_DC;
          src_sel2 = `OC8051_ASS_DC;
          alu_op = `OC8051_ALU_NOP;
          wr = 1'b0;
          psw_set = `OC8051_PS_NOT;
          cy_sel = `OC8051_CY_0;
          pc_wr = !eq;
          pc_sel = `OC8051_PIS_ALU;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DES;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          stb_i = 1'b1;          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          

        end
      `OC8051_JB : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_DC;
          src_sel2 = `OC8051_ASS_DC;
          alu_op = `OC8051_ALU_NOP;
          wr = 1'b0;
          psw_set = `OC8051_PS_NOT;
          cy_sel = `OC8051_CY_0;
          pc_wr = eq;
          pc_sel = `OC8051_PIS_ALU;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_BIT;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          stb_i = 1'b1;          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          

        end
      `OC8051_JBC : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_D;
          src_sel1 = `OC8051_ASS_DC;
          src_sel2 = `OC8051_ASS_DC;
          alu_op = `OC8051_ALU_NOP;
          wr = 1'b1;
          psw_set = `OC8051_PS_NOT;
          cy_sel = `OC8051_CY_0;
          pc_wr = eq;
          pc_sel = `OC8051_PIS_ALU;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_BIT;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b1;
          stb_i = 1'b1;          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          
          
        end
      `OC8051_JC : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_DC;
          src_sel2 = `OC8051_ASS_DC;
          alu_op = `OC8051_ALU_NOP;
          wr = 1'b0;
          psw_set = `OC8051_PS_NOT;
          cy_sel = `OC8051_CY_0;
          pc_wr = eq;
          pc_sel = `OC8051_PIS_ALU;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_CY;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          stb_i = 1'b1;          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          
          
        end
      `OC8051_JMP : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_DC;
          src_sel2 = `OC8051_ASS_DC;
          alu_op = `OC8051_ALU_NOP;
          wr = 1'b0;
          psw_set = `OC8051_PS_NOT;
          cy_sel = `OC8051_CY_0;
          pc_wr = `OC8051_PCW_Y;
          pc_sel = `OC8051_PIS_ALU;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_BIT;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          stb_i = 1'b1;          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          
          
        end
      `OC8051_JNB : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_DC;
          src_sel2 = `OC8051_ASS_DC;
          alu_op = `OC8051_ALU_NOP;
          wr = 1'b0;
          psw_set = `OC8051_PS_NOT;
          cy_sel = `OC8051_CY_0;
          pc_wr = !eq;
          pc_sel = `OC8051_PIS_ALU;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_BIT;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          stb_i = 1'b1;          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          
          
        end
      `OC8051_JNC : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_DC;
          src_sel2 = `OC8051_ASS_DC;
          alu_op = `OC8051_ALU_NOP;
          wr = 1'b0;
          psw_set = `OC8051_PS_NOT;
          cy_sel = `OC8051_CY_0;
          pc_wr = !eq;
          pc_sel = `OC8051_PIS_ALU;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_CY;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          stb_i = 1'b1;          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          
          
        end
      `OC8051_JNZ : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_DC;
          src_sel2 = `OC8051_ASS_DC;
          alu_op = `OC8051_ALU_NOP;
          wr = 1'b0;
          psw_set = `OC8051_PS_NOT;
          cy_sel = `OC8051_CY_0;
          pc_wr = !eq;
          pc_sel = `OC8051_PIS_ALU;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_AZ;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          stb_i = 1'b1;          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          
          
        end
      `OC8051_JZ : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_DC;
          src_sel2 = `OC8051_ASS_DC;
          alu_op = `OC8051_ALU_NOP;
          wr = 1'b0;
          psw_set = `OC8051_PS_NOT;
          cy_sel = `OC8051_CY_0;
          pc_wr = eq;
          pc_sel = `OC8051_PIS_ALU;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_AZ;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          stb_i = 1'b1;          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          

        end
      `OC8051_MOVC_DP :begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel2 = `OC8051_ASS_DC;
          alu_op = `OC8051_ALU_NOP;
          wr = 1'b1;
          psw_set = `OC8051_PS_NOT;
          cy_sel = `OC8051_CY_0;
          pc_wr = `OC8051_PCW_N;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP1;
          src_sel3 = `OC8051_AS3_DP;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          stb_i = 1'b1;          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          

        end
      `OC8051_MOVC_PC :begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_ACC;
          src_sel1 = `OC8051_ASS_IMM;
          src_sel2 = `OC8051_ASS_DC;
          alu_op = `OC8051_ALU_NOP;
          wr = 1'b1;
          psw_set = `OC8051_PS_NOT;
          cy_sel = `OC8051_CY_0;
          pc_wr = `OC8051_PCW_N;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_OP1;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          stb_i = 1'b1;          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          
        end
      `OC8051_SJMP : begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_DC;
          src_sel2 = `OC8051_ASS_DC;
          alu_op = `OC8051_ALU_NOP;
          wr = 1'b0;
          psw_set = `OC8051_PS_NOT;
          cy_sel = `OC8051_CY_0;
          pc_wr = `OC8051_PCW_Y;
          pc_sel = `OC8051_PIS_ALU;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          stb_i = 1'b1;          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          
        end
      `OC8051_DIV : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_B;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel2 = `OC8051_ASS_RAM;
          alu_op = `OC8051_ALU_DIV;
          wr = 1'b0;
          psw_set = `OC8051_PS_OV;
          cy_sel = `OC8051_CY_0;
          pc_wr = `OC8051_PCW_N;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          stb_i = 1'b1;          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          
        end
      `OC8051_MUL : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_B;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel2 = `OC8051_ASS_RAM;
          alu_op = `OC8051_ALU_MUL;
          wr = 1'b0;
          psw_set = `OC8051_PS_OV;
          cy_sel = `OC8051_CY_0;
          pc_wr = `OC8051_PCW_N;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_N;
          stb_i = 1'b1;          rom_addr_sel = `OC8051_RAS_PC;
          
        end
      default begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_DC;
          src_sel2 = `OC8051_ASS_DC;
          alu_op = `OC8051_ALU_NOP;
          wr = 1'b0;
          psw_set = `OC8051_PS_NOT;
          cy_sel = `OC8051_CY_0;
          pc_wr = `OC8051_PCW_N;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          stb_i = 1'b1;          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          
      end
    endcase

    2'b11:
    casex (op_cur)
      `OC8051_MOVC_DP :begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_DC;
          src_sel2 = `OC8051_ASS_DC;
          alu_op = `OC8051_ALU_NOP;
          wr = 1'b0;
          psw_set = `OC8051_PS_NOT;
          cy_sel = `OC8051_CY_0;
          pc_wr = `OC8051_PCW_N;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DP;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          stb_i = 1'b1;          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_DES;
          

        end
      `OC8051_MOVC_PC :begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_wr_sel = `OC8051_RWS_DC;
          src_sel1 = `OC8051_ASS_DC;
          src_sel2 = `OC8051_ASS_DC;
          alu_op = `OC8051_ALU_NOP;
          wr = 1'b0;
          psw_set = `OC8051_PS_NOT;
          cy_sel = `OC8051_CY_0;
          pc_wr = `OC8051_PCW_N;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_PC;
          comp_sel = `OC8051_CSS_DC;
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oc8051_decoder.v - 源码说明

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