pll.fit

PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛

-- MAX+plus II Compiler Fit File      
-- Version 10.0 9/14/2000             
-- Compiled: 05/27/2003 15:10:13      

-- Copyright (C) 1988-2000 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.

CHIP "pll"
BEGIN

    DEVICE = "EPM7032SLC44-5";

    "fi"                           : INPUT_PIN  = 4      ; -- LC1
    "fosc"                         : INPUT_PIN  = 43     ;
    "reset"                        : INPUT_PIN  = 5      ; -- LC2
    "ahead"                        : OUTPUT_PIN = 27     ; -- LC29
    "ck169"                        : OUTPUT_PIN = 24     ; -- LC32
    "d0"                           : OUTPUT_PIN = 28     ; -- LC28
    "d1"                           : OUTPUT_PIN = 29     ; -- LC27
    "d2"                           : OUTPUT_PIN = 31     ; -- LC26
    "lag"                          : OUTPUT_PIN = 26     ; -- LC30
    "ld"                           : OUTPUT_PIN = 25     ; -- LC31
    "q0"                           : OUTPUT_PIN = 41     ; -- LC17
    "q1"                           : OUTPUT_PIN = 33     ; -- LC24
    "q2"                           : OUTPUT_PIN = 40     ; -- LC18
    "q3"                           : OUTPUT_PIN = 39     ; -- LC19
    "q4"                           : OUTPUT_PIN = 37     ; -- LC21
    "q5"                           : OUTPUT_PIN = 36     ; -- LC22
    "u/d"                          : OUTPUT_PIN = 34     ; -- LC23
    "|edge:72|:1"                  : LOCATION   = LC25   ; -- PIN 32
    "|edge:72|:6"                  : LOCATION   = LC12   ; -- PIN 17  -- |edge:72|out
    ":50"                          : LOCATION   = LC8    ; -- PIN 12
    ":52"                          : LOCATION   = LC20   ; -- PIN 38
    ":59"                          : LOCATION   = LC4    ; -- PIN 7

END;

INTERNAL_INFO "pll"
BEGIN
	DEVICE = EPM7032SLC44-5;
	LC32    : LORAX = "G58R0";
	LC31    : LORAX = "G57R0";
	LC23    : LORAX = "G32R0,PA12R0C1";
	LC26    : LORAX = "G39R0,PA25R0C1";
	LC27    : LORAX = "G40R0,PA24R0C1";
	LC28    : LORAX = "G41R0,PA22R0C1";
	LC29    : LORAX = "G55R0";
	LC30    : LORAX = "G56R0";
	LC22    : LORAX = "G31R0,PA14R0C1";
	LC21    : LORAX = "G30R0,PA16R0C1";
	LC19    : LORAX = "G15R0,PA3R0C1";
	LC18    : LORAX = "G14R0,PA5R0C1";
	LC24    : LORAX = "G33R0,PA10R0C1";
	LC17    : LORAX = "G13R0,PA7R0C1";
	OH0R0P4 : LORAX = "G43R0,PA20R0C0,PA20R0C1";
	LC4     : LORAX = "G12R0,PA0R0C1";
	LC8     : LORAX = "G29R0,PA9R0C0";
	LC12    : LORAX = "G37R0,PA26R0C1";
	LC25    : LORAX = "G38R0,PA18R0C0";
	LC20    : LORAX = "G16R0,PA1R0C1";
	OH1R0P5 : LORAX = "G44R0,PA19R0C1";
END;