razzle.vhd

使用vhdl语言在altera公司的up3板上产生vga信号

--
-- Razzle generates a simple fractal type color image on a VGA monitor
--
-- Jim Hamblen, Georgia Tech School of ECE
--
library IEEE;
use  IEEE.STD_LOGIC_1164.all;
use  IEEE.STD_LOGIC_ARITH.all;
use  IEEE.STD_LOGIC_UNSIGNED.all;

entity razzle is

   port( signal Clock_48Mhz : in std_logic;
        signal Red,Green,Blue : out std_logic;
        signal Horiz_sync,Vert_sync : inout std_logic);
       		
end razzle;

architecture behavior of razzle is

-- Video Display Signals   
signal H_count,V_count: std_logic_vector(10 Downto 0);
signal Red_Data, Green_Data, Blue_Data : std_logic;
signal sum, rowdist, coldist : std_logic_vector(10 DOWNTO 0);
signal nrowdist, ncoldist : std_logic_vector(10 DOWNTO 0);
signal dither: std_logic_vector(3 DOWNTO 0);
signal video_on, video_on_h, video_on_v, clock_enable : std_logic;

begin           
-- Colors for pixel data on video signal
Red_Data <= sum(2);
Green_Data <= sum(3);
Blue_Data <= sum(4);

-- turn off color (black) at screen edges and during retrace with video_on
Red <=   Red_Data and video_on;
Green <= Green_Data and video_on;
Blue <=  Blue_Data and video_on;

-- video_on turns off pixel color data when not in the pixel view area
video_on <= video_on_H and video_on_V;

-- This process computes a color to each pixel as the image is scanned by the monitor
-- no pixel memory is used. The pixel row and col address is used to compute a color.
FRACTAL_COMPUTE: Process (clock_48Mhz)
Begin
 IF (clock_48Mhz'event) and (clock_48Mhz='1') Then
 	IF video_on = '1'  THEN
		If V_count > 240 THEN
			rowdist <= V_count -240;
		else
			rowdist <= 240 - V_count;
		END IF;
		IF rowdist > 120 THEN
			nrowdist <= rowdist -120;
		else
			nrowdist <= 120 - rowdist;
		end if;	
		If H_count > 320 THEN
			coldist <= H_count -320;
		else
			coldist <= 320 - H_count;
		end if;
		if coldist >160 THEN
			ncoldist <= coldist -160;
		else
			ncoldist <= 160 - coldist;
		END IF;
-- sum assigns a color to each pixel based on it's row + col address
-- dither makes colors change on each new image scan
-- this make the image appear to move	
	sum <= nrowdist + ncoldist + ( dither & "00") ;
	END If;
end if;
end process FRACTAL_COMPUTE;


process
begin
	wait until Vert_Sync'event and Vert_Sync = '1';
			dither <= dither + 1;
end process;

--Generate Horizontal and Vertical Timing Signals for Video Signal
--For details see Rapid Prototyping of Digital Systems Chapter 9
VIDEO_DISPLAY: Process
Begin
Wait until(Clock_48Mhz'Event) and (Clock_48Mhz='1');
-- Clock enable used for a 24Mhz video clock rate
-- 640 by 480 display mode needs close to a 25Mhz pixel clock
-- 24Mhz should work on most new monitors
clock_enable <= NOT clock_enable;
-- H_count counts pixels (640 + extra time for sync signals)
--
--   <-Clock out RGB Pixel Row Data ->   <-H Sync->
--   ------------------------------------__________--------
--   0                           640   659       755    799
--
If clock_enable = '1' then
If (H_count >= 799) then
   H_count <= B"00000000000";
Else
   H_count <= H_count + 1;
End if;

--Generate Horizontal Sync Signal
If (H_count <= 755) and (H_count >= 659) Then
   Horiz_Sync <= '0';
ELSE
   Horiz_Sync <= '1';
End if;

--V_count counts rows of pixels (480 + extra time for sync signals)
--
--  <---- 480 Horizontal Syncs (pixel rows) -->  ->V Sync<-
--  -----------------------------------------------_______------------
--  0                                       480    493-494          524
--
If (V_count >= 524) and (H_count >= 699) then
   V_count <= B"00000000000";
Else If (H_count = 699) Then
   V_count <= V_count + 1;
End if;
End if;

-- Generate Vertical Sync Signal
If (V_count <= 494) and (V_count >= 493) Then
   Vert_Sync <= '0';
ELSE
   Vert_Sync <= '1';
End if;

-- Generate Video on Screen Signals for Pixel Data
If (H_count <= 639) Then
   video_on_H <= '1';
ELSE
   video_on_H <= '0';
End if;

If (V_count <= 479) Then
   video_on_V <= '1';
ELSE
   video_on_V <= '0';
End if;

End if;
end process VIDEO_DISPLAY;

end behavior;