sin_rom.flow.rpt

来自「该源码为几个正弦ROM,已经编译并通过,可以直接下载,不需要,内部含有正弦ROM」· RPT 代码 · 共 88 行

Flow report for SIN_ROM
Sat Jul 23 16:15:14 2005
Version 5.0 Build 148 04/26/2005 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Elapsed Time
  5. Flow Log



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+-------------------------------------------------------------------+
; Flow Summary                                                      ;
+-------------------------+-----------------------------------------+
; Flow Status             ; Successful - Sat Jul 23 16:15:14 2005   ;
; Quartus II Version      ; 5.0 Build 148 04/26/2005 SJ Web Edition ;
; Revision Name           ; SIN_ROM                                 ;
; Top-level Entity Name   ; sin_rom                                 ;
; Family                  ; ACEX1K                                  ;
; Device                  ; EP1K30TC144-3                           ;
; Timing Models           ; Final                                   ;
; Met timing requirements ; Yes                                     ;
; Total logic elements    ; 0 / 1,728 ( 0 % )                       ;
; Total pins              ; 19 / 102 ( 18 % )                       ;
; Total memory bits       ; 8,192 / 24,576 ( 33 % )                 ;
; Total PLLs              ; 0                                       ;
+-------------------------+-----------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 07/23/2005 16:14:54 ;
; Main task         ; Compilation         ;
; Revision Name     ; SIN_ROM             ;
+-------------------+---------------------+


+-------------------------------------+
; Flow Elapsed Time                   ;
+----------------------+--------------+
; Module Name          ; Elapsed Time ;
+----------------------+--------------+
; Analysis & Synthesis ; 00:00:04     ;
; Fitter               ; 00:00:08     ;
; Assembler            ; 00:00:02     ;
; Timing Analyzer      ; 00:00:03     ;
; Total                ; 00:00:17     ;
+----------------------+--------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off SIN_ROM -c SIN_ROM
quartus_fit --read_settings_files=off --write_settings_files=off SIN_ROM -c SIN_ROM
quartus_asm --read_settings_files=off --write_settings_files=off SIN_ROM -c SIN_ROM
quartus_tan --read_settings_files=off --write_settings_files=off SIN_ROM -c SIN_ROM