sin_rom.fit.talkback.xml

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<!--
This XML file (created on Sat Jul 23 16:15:06 2005) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to www.altera.com/products/software/download/dnl-download_license.html
-->
<talkback>
<ver>5.0</ver>
<schema>quartus_version_5.0_build_148.xsd</schema><license>
	<host_id>00112f2abe5d</host_id>
	<nic_id>00112f2abe5d</nic_id>
	<cdrive_id>90790395</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>5.0</version>
	<build>Build 148</build>
	<module>quartus_fit.exe</module>
	<edition>Web Edition</edition>
	<compilation_end_time>Sat Jul 23 16:15:07 2005</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>2</proc_count>
		<cpu_freq units="MHz">2798</cpu_freq>
	</cpu>
	<ram units="MB">512</ram>
</machine>
<top_file>E:/lhh/mokuai/rom/SIN_ROM</top_file>
<resource_usage_summary>
	<rsc name="Registers" util="0" max=" 1728 " type="int">0 </rsc>
	<rsc name="Total LABs" util="0" max=" 216 " type="int">0 </rsc>
	<rsc name="Logic elements in carry chains" type="int">0</rsc>
	<rsc name="User inserted logic elements" type="int">0</rsc>
	<rsc name="I/O pins" util="18" max=" 102 " type="int">19 </rsc>
	<rsc name="-- Clock pins" type="int">2</rsc>
	<rsc name="-- Dedicated input pins" util="100" max=" 4 " type="int">4 </rsc>
	<rsc name="Global signals" type="int">1</rsc>
	<rsc name="EABs" util="33" max=" 6 " type="int">2 </rsc>
	<rsc name="Total memory bits" util="33" max=" 24576 " type="int">8192 </rsc>
	<rsc name="Total RAM block bits" util="33" max=" 24576 " type="int">8192 </rsc>
	<rsc name="Maximum fan-out node" type="text">inclock</rsc>
	<rsc name="Maximum fan-out" type="int">8</rsc>
	<rsc name="Total fan-out" type="int">96</rsc>
	<rsc name="Average fan-out" type="float">3.56</rsc>
</resource_usage_summary>
<ram_summary>
	<row>
		<name>altsyncram:altsyncram_component|altrom:rom|content</name>
		<mode>ROM</mode>
		<port_a_depth>1024</port_a_depth>
		<port_a_width>8</port_a_width>
		<port_a_input_registers>no</port_a_input_registers>
		<port_a_output_registers>no</port_a_output_registers>
		<size>0</size>
		<meabs>2</meabs>
		<mif>./dds_sin.mif</mif>
		<location>ESB_C, ESB_A</location>
	</row>
</ram_summary>
<mep_data>
	<command_line>quartus_fit --read_settings_files=off --write_settings_files=off SIN_ROM -c SIN_ROM</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<messages>
	<info>Info: Quartus II Fitter was successful. 0 errors, 0 warnings</info>
	<info>Info: Elapsed time: 00:00:08</info>
	<info>Info: Processing ended: Sat Jul 23 16:15:06 2005</info>
	<info>Info: Fitter routing operations ending: elapsed time is 00:00:00</info>
	<info>Info: Fitter routing operations beginning</info>
</messages>
<fitter_settings>
	<row>
		<option>Device</option>
		<setting>EP1K30TC144-3</setting>
	</row>
	<row>
		<option>Use smart compilation</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Placement Effort Multiplier</option>
		<setting>1.0</setting>
		<default_value>1.0</default_value>
	</row>
	<row>
		<option>Router Effort Multiplier</option>
		<setting>1.0</setting>
		<default_value>1.0</default_value>
	</row>
	<row>
		<option>Optimize Timing</option>
		<setting>Normal compilation</setting>
		<default_value>Normal compilation</default_value>
	</row>
	<row>
		<option>Optimize IOC Register Placement for Timing</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Limit to One Fitting Attempt</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Final Placement Optimizations</option>
		<setting>Automatically</setting>
		<default_value>Automatically</default_value>
	</row>
	<row>
		<option>Fitter Initial Placement Seed</option>
		<setting>1</setting>
		<default_value>1</default_value>
	</row>
	<row>
		<option>Slow Slew Rate</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>PCI I/O</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Auto Global Memory Control Signals</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Logic Cell Insertion - Individual Logic Cells</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Logic Cell Insertion - I/Os Fed By Carry or Cascade Chains</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Fitter Effort</option>
		<setting>Auto Fit</setting>
		<default_value>Auto Fit</default_value>
	</row>
	<row>
		<option>Auto Global Clock</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Global Output Enable</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Global Register Control Signals</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
</fitter_settings>
<fitter_device_options>
	<row>
		<option>Enable user-supplied start-up clock (CLKUSR)</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Enable device-wide reset (DEV_CLRn)</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Enable device-wide output enable (DEV_OE)</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Enable INIT_DONE output</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Configuration scheme</option>
		<setting>Passive Serial</setting>
	</row>
	<row>
		<option>Reserve all unused pins</option>
		<setting>As output driving ground</setting>
	</row>
	<row>
		<option>Base pin-out file on sameframe device</option>
		<setting>Off</setting>
	</row>
</fitter_device_options>
<input_pins>
	<row>
		<name>inclock</name>
		<pin__>55</pin__>
		<fan_out>8</fan_out>
		<global>yes</global>
		<i_o_register>no</i_o_register>
		<use_local_routing_input>no</use_local_routing_input>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_ce>no</single_pin_ce>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>address[0]</name>
		<pin__>126</pin__>
		<fan_out>8</fan_out>
		<global>no</global>
		<i_o_register>no</i_o_register>
		<use_local_routing_input>no</use_local_routing_input>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_ce>no</single_pin_ce>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>address[1]</name>
		<pin__>124</pin__>
		<fan_out>8</fan_out>
		<global>no</global>
		<i_o_register>no</i_o_register>
		<use_local_routing_input>no</use_local_routing_input>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_ce>no</single_pin_ce>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>address[2]</name>
		<pin__>54</pin__>
		<fan_out>8</fan_out>
		<global>no</global>
		<i_o_register>no</i_o_register>
		<use_local_routing_input>no</use_local_routing_input>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_ce>no</single_pin_ce>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>address[3]</name>
		<pin__>56</pin__>
		<fan_out>8</fan_out>
		<global>no</global>
		<i_o_register>no</i_o_register>
		<use_local_routing_input>no</use_local_routing_input>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>