sin_rom.hif

来自「该源码为几个正弦ROM,已经编译并通过,可以直接下载,不需要,内部含有正弦ROM」· HIF 代码 · 共 952 行

HIF
952 行
字号 
Version 5.0 Build 148 04/26/2005 SJ Web Edition
2
24
OFF
OFF
OFF
OFF
OFF
FV_OFF
VRSM_ON
VHSM_ON
0
# entity
altsyncram
# case_insensitive
# source_file
d:|altera|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|SIN_ROM.(1).cnf
db|SIN_ROM.(1).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
10
PARAMETER_DEC
USR
WIDTHAD_A
10
PARAMETER_DEC
USR
NUMWORDS_A
1024
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
./dds_sin.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
ACEX1K
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_a8
q_a9
}
# include_file {
d:|altera|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
d:|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
d:|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
d:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
d:|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
d:|altera|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
d:|altera|quartus50|libraries|megafunctions|altrom.inc
1107573422
d:|altera|quartus50|libraries|megafunctions|altram.inc
1107573384
d:|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
d:|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
}
# end
# entity
altrom
# case_insensitive
# source_file
d:|altera|quartus50|libraries|megafunctions|altrom.tdf
1114012438
6
# storage
db|SIN_ROM.(2).cnf
db|SIN_ROM.(2).cnf
# user_parameter {
WIDTH
10
PARAMETER_UNKNOWN
USR
AD_WIDTH
10
PARAMETER_UNKNOWN
USR
NUMWORDS
1024
PARAMETER_UNKNOWN
USR
FILE
./dds_sin.mif
PARAMETER_UNKNOWN
USR
REGISTERINPUTMODE
ALL
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
ACEX1K
PARAMETER_UNKNOWN
USR
SUPPRESS_MEMORY_CONVERSION_WARNINGS
OFF
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
address0
address1
address2
address3
address4
address5
address6
address7
address8
address9
clocki
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
}
# include_file {
d:|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
d:|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
d:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
d:|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
d:|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
d:|altera|quartus50|libraries|others|maxplus2|memmodes.inc
1107579370
}
# memory_file {
.|dds_sin.mif
996117614
}
# end
# entity
altsyncram
# case_insensitive
# source_file
d:|altera|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|SIN_ROM.(3).cnf
db|SIN_ROM.(3).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
10
PARAMETER_DEC
USR
WIDTHAD_A
10
PARAMETER_DEC
USR
NUMWORDS_A
1024
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
./dds_sin.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
ACEX1K
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
}
# include_file {
d:|altera|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
d:|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
d:|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
d:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
d:|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
d:|altera|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
d:|altera|quartus50|libraries|megafunctions|altrom.inc
1107573422
d:|altera|quartus50|libraries|megafunctions|altram.inc
1107573384
d:|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
d:|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
}
# end
# entity
sin_rom
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
SIN_ROM.VHD
1121845814
4
# storage
db|SIN_ROM.(0).cnf
db|SIN_ROM.(0).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
|
}
# end
# entity
altsyncram
# case_insensitive
# source_file
d:|altera|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|SIN_ROM.(4).cnf
db|SIN_ROM.(4).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_DEC
USR
WIDTHAD_A
10
PARAMETER_DEC
USR
NUMWORDS_A
1024
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
./dds_sin.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
ACEX1K
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
}
# include_file {
d:|altera|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
d:|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
d:|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
d:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
d:|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
d:|altera|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
d:|altera|quartus50|libraries|megafunctions|altrom.inc
1107573422
d:|altera|quartus50|libraries|megafunctions|altram.inc
1107573384
d:|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
d:|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
}
# hierarchies {
altsyncram:altsyncram_component
}
# end
# entity
altrom
# case_insensitive
# source_file
d:|altera|quartus50|libraries|megafunctions|altrom.tdf
1114012438
6
# storage
db|SIN_ROM.(5).cnf
db|SIN_ROM.(5).cnf
# user_parameter {
WIDTH
8
PARAMETER_UNKNOWN
USR
AD_WIDTH
10
PARAMETER_UNKNOWN
USR
NUMWORDS
1024
PARAMETER_UNKNOWN
USR
FILE
./dds_sin.mif
PARAMETER_UNKNOWN
USR
REGISTERINPUTMODE
ALL
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
ACEX1K
PARAMETER_UNKNOWN
USR
SUPPRESS_MEMORY_CONVERSION_WARNINGS
OFF
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
address0
address1
address2
address3
address4
address5
address6
address7
address8
address9
clocki
q0
q1
q2
q3
q4
q5
q6
q7
}
# include_file {
d:|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
d:|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
d:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
d:|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
d:|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
d:|altera|quartus50|libraries|others|maxplus2|memmodes.inc
1107579370
}
# memory_file {
.|dds_sin.mif
996117614
}
# hierarchies {
altsyncram:altsyncram_component|altrom:rom
}
# end
# complete

sin_rom.hif - 源码说明

本页面展示了「该源码为几个正弦ROM,已经编译并通过,可以直接下载,不需要,内部含有正弦ROM表,还有ROM的宏模块」中的 sin_rom.hif 源码文件，采用 HIF 编程语言编写，共 952 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

虫虫开发者社区收录了大量与正弦ROM相关的技术资源，包括源代码、技术文档、电路图等，是电子工程师和嵌入式开发者的专业学习平台。

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