datarom.tan.rpt

该源码为几个正弦ROM,已经编译并通过,可以直接下载,不需要,内部含有正弦ROM表,还有ROM的宏模块

; N/A           ; None        ; -0.700 ns ; address[4] ; lpm_rom:lpm_rom_component|altrom:srom|q[5]~reg_ra4 ; inclock  ;
; N/A           ; None        ; -0.700 ns ; address[4] ; lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra4 ; inclock  ;
; N/A           ; None        ; -0.700 ns ; address[4] ; lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra4 ; inclock  ;
; N/A           ; None        ; -0.700 ns ; address[3] ; lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra3 ; inclock  ;
; N/A           ; None        ; -0.700 ns ; address[3] ; lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra3 ; inclock  ;
; N/A           ; None        ; -0.700 ns ; address[3] ; lpm_rom:lpm_rom_component|altrom:srom|q[2]~reg_ra3 ; inclock  ;
; N/A           ; None        ; -0.700 ns ; address[3] ; lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra3 ; inclock  ;
; N/A           ; None        ; -0.700 ns ; address[3] ; lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra3 ; inclock  ;
; N/A           ; None        ; -0.700 ns ; address[3] ; lpm_rom:lpm_rom_component|altrom:srom|q[5]~reg_ra3 ; inclock  ;
; N/A           ; None        ; -0.700 ns ; address[3] ; lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra3 ; inclock  ;
; N/A           ; None        ; -0.700 ns ; address[3] ; lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra3 ; inclock  ;
; N/A           ; None        ; -0.700 ns ; address[2] ; lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra2 ; inclock  ;
; N/A           ; None        ; -0.700 ns ; address[2] ; lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra2 ; inclock  ;
; N/A           ; None        ; -0.700 ns ; address[2] ; lpm_rom:lpm_rom_component|altrom:srom|q[2]~reg_ra2 ; inclock  ;
; N/A           ; None        ; -0.700 ns ; address[2] ; lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra2 ; inclock  ;
; N/A           ; None        ; -0.700 ns ; address[2] ; lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra2 ; inclock  ;
; N/A           ; None        ; -0.700 ns ; address[2] ; lpm_rom:lpm_rom_component|altrom:srom|q[5]~reg_ra2 ; inclock  ;
; N/A           ; None        ; -0.700 ns ; address[2] ; lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra2 ; inclock  ;
; N/A           ; None        ; -0.700 ns ; address[2] ; lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra2 ; inclock  ;
; N/A           ; None        ; -0.700 ns ; address[1] ; lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra1 ; inclock  ;
; N/A           ; None        ; -0.700 ns ; address[1] ; lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra1 ; inclock  ;
; N/A           ; None        ; -0.700 ns ; address[1] ; lpm_rom:lpm_rom_component|altrom:srom|q[2]~reg_ra1 ; inclock  ;
; N/A           ; None        ; -0.700 ns ; address[1] ; lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra1 ; inclock  ;
; N/A           ; None        ; -0.700 ns ; address[1] ; lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra1 ; inclock  ;
; N/A           ; None        ; -0.700 ns ; address[1] ; lpm_rom:lpm_rom_component|altrom:srom|q[5]~reg_ra1 ; inclock  ;
; N/A           ; None        ; -0.700 ns ; address[1] ; lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra1 ; inclock  ;
; N/A           ; None        ; -0.700 ns ; address[1] ; lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra1 ; inclock  ;
; N/A           ; None        ; -0.700 ns ; address[0] ; lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra0 ; inclock  ;
; N/A           ; None        ; -0.700 ns ; address[0] ; lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra0 ; inclock  ;
; N/A           ; None        ; -0.700 ns ; address[0] ; lpm_rom:lpm_rom_component|altrom:srom|q[2]~reg_ra0 ; inclock  ;
; N/A           ; None        ; -0.700 ns ; address[0] ; lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra0 ; inclock  ;
; N/A           ; None        ; -0.700 ns ; address[0] ; lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra0 ; inclock  ;
; N/A           ; None        ; -0.700 ns ; address[0] ; lpm_rom:lpm_rom_component|altrom:srom|q[5]~reg_ra0 ; inclock  ;
; N/A           ; None        ; -0.700 ns ; address[0] ; lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra0 ; inclock  ;
; N/A           ; None        ; -0.700 ns ; address[0] ; lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0 ; inclock  ;
; N/A           ; None        ; -4.800 ns ; address[6] ; lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra6 ; inclock  ;
; N/A           ; None        ; -4.800 ns ; address[6] ; lpm_rom:lpm_rom_component|altrom:srom|q[2]~reg_ra6 ; inclock  ;
; N/A           ; None        ; -4.800 ns ; address[6] ; lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra6 ; inclock  ;
; N/A           ; None        ; -4.800 ns ; address[6] ; lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra6 ; inclock  ;
; N/A           ; None        ; -4.900 ns ; address[6] ; lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra6 ; inclock  ;
; N/A           ; None        ; -4.900 ns ; address[6] ; lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra6 ; inclock  ;
; N/A           ; None        ; -4.900 ns ; address[6] ; lpm_rom:lpm_rom_component|altrom:srom|q[5]~reg_ra6 ; inclock  ;
; N/A           ; None        ; -4.900 ns ; address[6] ; lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra6 ; inclock  ;
; N/A           ; None        ; -5.100 ns ; address[5] ; lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra5 ; inclock  ;
; N/A           ; None        ; -5.100 ns ; address[5] ; lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra5 ; inclock  ;
; N/A           ; None        ; -5.100 ns ; address[5] ; lpm_rom:lpm_rom_component|altrom:srom|q[5]~reg_ra5 ; inclock  ;
; N/A           ; None        ; -5.100 ns ; address[5] ; lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra5 ; inclock  ;
; N/A           ; None        ; -5.200 ns ; address[5] ; lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra5 ; inclock  ;
; N/A           ; None        ; -5.200 ns ; address[5] ; lpm_rom:lpm_rom_component|altrom:srom|q[2]~reg_ra5 ; inclock  ;
; N/A           ; None        ; -5.200 ns ; address[5] ; lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra5 ; inclock  ;
; N/A           ; None        ; -5.200 ns ; address[5] ; lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra5 ; inclock  ;
; N/A           ; None        ; -5.700 ns ; address[7] ; lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra7 ; inclock  ;
; N/A           ; None        ; -5.700 ns ; address[7] ; lpm_rom:lpm_rom_component|altrom:srom|q[2]~reg_ra7 ; inclock  ;
; N/A           ; None        ; -5.700 ns ; address[7] ; lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra7 ; inclock  ;
; N/A           ; None        ; -5.700 ns ; address[7] ; lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra7 ; inclock  ;
; N/A           ; None        ; -5.800 ns ; address[7] ; lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra7 ; inclock  ;
; N/A           ; None        ; -5.800 ns ; address[7] ; lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra7 ; inclock  ;
; N/A           ; None        ; -5.800 ns ; address[7] ; lpm_rom:lpm_rom_component|altrom:srom|q[5]~reg_ra7 ; inclock  ;
; N/A           ; None        ; -5.800 ns ; address[7] ; lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra7 ; inclock  ;
+---------------+-------------+-----------+------------+----------------------------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Web Edition
    Info: Processing started: Wed Jul 20 16:45:16 2005
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off datarom -c datarom
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "inclock" is an undefined clock
Info: No valid register-to-register data paths exist for clock "inclock"
Info: tsu for memory "lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra7" (data pin = "address[7]", clock pin = "inclock") is 7.500 ns
    Info: + Longest pin to memory delay is 8.700 ns
        Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_114; Fanout = 8; PIN Node = 'address[7]'
        Info: 2: + IC(3.000 ns) + CELL(0.800 ns) = 8.700 ns; Loc. = EC11_D; Fanout = 1; MEM Node = 'lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra7'
        Info: Total cell delay = 5.700 ns ( 65.52 % )
        Info: Total interconnect delay = 3.000 ns ( 34.48 % )
    Info: + Micro setup delay of destination is 1.200 ns
    Info: - Shortest clock path from clock "inclock" to destination memory is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 64; CLK Node = 'inclock'
        Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = EC11_D; Fanout = 1; MEM Node = 'lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra7'
        Info: Total cell delay = 2.000 ns ( 83.33 % )
        Info: Total interconnect delay = 0.400 ns ( 16.67 % )
Info: tco from clock "inclock" to destination pin "q[7]" through memory "lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0" is 18.600 ns
    Info: + Longest clock path from clock "inclock" to source memory is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 64; CLK Node = 'inclock'
        Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = EC12_D; Fanout = 1; MEM Node = 'lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0'
        Info: Total cell delay = 2.000 ns ( 83.33 % )
        Info: Total interconnect delay = 0.400 ns ( 16.67 % )
    Info: + Micro clock to output delay of source is 0.400 ns
    Info: + Longest memory to pin delay is 15.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = EC12_D; Fanout = 1; MEM Node = 'lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0'
        Info: 2: + IC(0.000 ns) + CELL(4.400 ns) = 4.400 ns; Loc. = EC12_D; Fanout = 1; MEM Node = 'lpm_rom:lpm_rom_component|altrom:srom|q[7]~mem_cell_ra0'
        Info: 3: + IC(0.000 ns) + CELL(1.400 ns) = 5.800 ns; Loc. = EC12_D; Fanout = 1; MEM Node = 'lpm_rom:lpm_rom_component|altrom:srom|q[7]'
        Info: 4: + IC(3.700 ns) + CELL(6.300 ns) = 15.800 ns; Loc. = PIN_14; Fanout = 0; PIN Node = 'q[7]'
        Info: Total cell delay = 12.100 ns ( 76.58 % )
        Info: Total interconnect delay = 3.700 ns ( 23.42 % )
Info: th for memory "lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra4" (data pin = "address[4]", clock pin = "inclock") is -0.700 ns
    Info: + Longest clock path from clock "inclock" to destination memory is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 64; CLK Node = 'inclock'
        Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = EC1_D; Fanout = 1; MEM Node = 'lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra4'
        Info: Total cell delay = 2.000 ns ( 83.33 % )
        Info: Total interconnect delay = 0.400 ns ( 16.67 % )
    Info: + Micro hold delay of destination is 0.500 ns
    Info: - Shortest pin to memory delay is 3.600 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_125; Fanout = 8; PIN Node = 'address[4]'
        Info: 2: + IC(0.800 ns) + CELL(0.800 ns) = 3.600 ns; Loc. = EC1_D; Fanout = 1; MEM Node = 'lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra4'
        Info: Total cell delay = 2.800 ns ( 77.78 % )
        Info: Total interconnect delay = 0.800 ns ( 22.22 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Jul 20 16:45:17 2005
    Info: Elapsed time: 00:00:02