datarom.tan.rpt

该源码为几个正弦ROM,已经编译并通过,可以直接下载,不需要,内部含有正弦ROM表,还有ROM的宏模块

Timing Analyzer report for datarom
Wed Jul 20 16:45:17 2005
Version 5.0 Build 148 04/26/2005 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. tsu
  6. tco
  7. th
  8. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                             ;
+------------------------------+-------+---------------+-------------+----------------------------------------------------+----------------------------------------------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From                                               ; To                                                 ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+----------------------------------------------------+----------------------------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 7.500 ns    ; address[7]                                         ; lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra7 ;            ; inclock  ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 18.600 ns   ; lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra7 ; q[7]                                               ; inclock    ;          ; 0            ;
; Worst-case th                ; N/A   ; None          ; -0.700 ns   ; address[0]                                         ; lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0 ;            ; inclock  ; 0            ;
; Total number of failed paths ;       ;               ;             ;                                                    ;                                                    ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+----------------------------------------------------+----------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1K30TC144-3      ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; inclock         ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+----------------------------------------------------------------------------------------------------------------+
; tsu                                                                                                            ;
+-------+--------------+------------+------------+----------------------------------------------------+----------+
; Slack ; Required tsu ; Actual tsu ; From       ; To                                                 ; To Clock ;
+-------+--------------+------------+------------+----------------------------------------------------+----------+
; N/A   ; None         ; 7.500 ns   ; address[7] ; lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra7 ; inclock  ;
; N/A   ; None         ; 7.500 ns   ; address[7] ; lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra7 ; inclock  ;
; N/A   ; None         ; 7.500 ns   ; address[7] ; lpm_rom:lpm_rom_component|altrom:srom|q[5]~reg_ra7 ; inclock  ;
; N/A   ; None         ; 7.500 ns   ; address[7] ; lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra7 ; inclock  ;
; N/A   ; None         ; 7.400 ns   ; address[7] ; lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra7 ; inclock  ;
; N/A   ; None         ; 7.400 ns   ; address[7] ; lpm_rom:lpm_rom_component|altrom:srom|q[2]~reg_ra7 ; inclock  ;
; N/A   ; None         ; 7.400 ns   ; address[7] ; lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra7 ; inclock  ;
; N/A   ; None         ; 7.400 ns   ; address[7] ; lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra7 ; inclock  ;
; N/A   ; None         ; 6.900 ns   ; address[5] ; lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra5 ; inclock  ;
; N/A   ; None         ; 6.900 ns   ; address[5] ; lpm_rom:lpm_rom_component|altrom:srom|q[2]~reg_ra5 ; inclock  ;
; N/A   ; None         ; 6.900 ns   ; address[5] ; lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra5 ; inclock  ;
; N/A   ; None         ; 6.900 ns   ; address[5] ; lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra5 ; inclock  ;
; N/A   ; None         ; 6.800 ns   ; address[5] ; lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra5 ; inclock  ;
; N/A   ; None         ; 6.800 ns   ; address[5] ; lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra5 ; inclock  ;
; N/A   ; None         ; 6.800 ns   ; address[5] ; lpm_rom:lpm_rom_component|altrom:srom|q[5]~reg_ra5 ; inclock  ;
; N/A   ; None         ; 6.800 ns   ; address[5] ; lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra5 ; inclock  ;
; N/A   ; None         ; 6.600 ns   ; address[6] ; lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra6 ; inclock  ;
; N/A   ; None         ; 6.600 ns   ; address[6] ; lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra6 ; inclock  ;
; N/A   ; None         ; 6.600 ns   ; address[6] ; lpm_rom:lpm_rom_component|altrom:srom|q[5]~reg_ra6 ; inclock  ;
; N/A   ; None         ; 6.600 ns   ; address[6] ; lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra6 ; inclock  ;
; N/A   ; None         ; 6.500 ns   ; address[6] ; lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra6 ; inclock  ;
; N/A   ; None         ; 6.500 ns   ; address[6] ; lpm_rom:lpm_rom_component|altrom:srom|q[2]~reg_ra6 ; inclock  ;
; N/A   ; None         ; 6.500 ns   ; address[6] ; lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra6 ; inclock  ;
; N/A   ; None         ; 6.500 ns   ; address[6] ; lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra6 ; inclock  ;
; N/A   ; None         ; 2.400 ns   ; address[4] ; lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra4 ; inclock  ;
; N/A   ; None         ; 2.400 ns   ; address[4] ; lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra4 ; inclock  ;
; N/A   ; None         ; 2.400 ns   ; address[4] ; lpm_rom:lpm_rom_component|altrom:srom|q[2]~reg_ra4 ; inclock  ;
; N/A   ; None         ; 2.400 ns   ; address[4] ; lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra4 ; inclock  ;
; N/A   ; None         ; 2.400 ns   ; address[4] ; lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra4 ; inclock  ;
; N/A   ; None         ; 2.400 ns   ; address[4] ; lpm_rom:lpm_rom_component|altrom:srom|q[5]~reg_ra4 ; inclock  ;