📄 sin_rom.map.rpt
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; -- Total 0-input functions ; 0 ;
; Combinational cells for routing ; 0 ;
; Total registers ; 0 ;
; I/O pins ; 19 ;
; Total memory bits ; 8192 ;
; Maximum fan-out node ; inclock ;
; Maximum fan-out ; 8 ;
; Total fan-out ; 96 ;
; Average fan-out ; 3.56 ;
+---------------------------------+-----------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+--------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+-----------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+--------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+-----------------------------------------------------+
; |sin_rom ; 0 (0) ; 0 ; 8192 ; 19 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |sin_rom ;
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 ; 8192 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |sin_rom|altsyncram:altsyncram_component ;
; |altrom:rom| ; 0 (0) ; 0 ; 8192 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |sin_rom|altsyncram:altsyncram_component|altrom:rom ;
+--------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+-----------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+----------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+----------------------------------------------------+------+--------------+--------------+--------------+--------------+------+---------------+
; Name ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+----------------------------------------------------+------+--------------+--------------+--------------+--------------+------+---------------+
; altsyncram:altsyncram_component|altrom:rom|content ; ROM ; 1024 ; 8 ; -- ; -- ; 8192 ; ./dds_sin.mif ;
+----------------------------------------------------+------+--------------+--------------+--------------+--------------+------+---------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 0 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: altsyncram:altsyncram_component ;
+------------------------------------+---------------+-------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+---------------+-------------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; OPERATION_MODE ; ROM ; Untyped ;
; WIDTH_A ; 8 ; Integer ;
; WIDTHAD_A ; 10 ; Integer ;
; NUMWORDS_A ; 1024 ; Integer ;
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 1 ; Untyped ;
; WIDTHAD_B ; 1 ; Untyped ;
; NUMWORDS_B ; 1 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Integer ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; INIT_FILE ; ./dds_sin.mif ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; DEVICE_FAMILY ; ACEX1K ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
+------------------------------------+---------------+-------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/lhh/mokuai/rom/SIN_ROM.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.0 Build 148 04/26/2005 SJ Web Edition
Info: Processing started: Sat Jul 23 16:14:54 2005
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off SIN_ROM -c SIN_ROM
Info: Found 2 design units, including 1 entities, in source file SIN_ROM.VHD
Info: Found design unit 1: sin_rom-SYN
Info: Found entity 1: sin_rom
Info: Elaborating entity "SIN_ROM" for the top level hierarchy
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/altsyncram.tdf
Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/altrom.tdf
Info: Found entity 1: altrom
Info: Elaborating entity "altrom" for hierarchy "altsyncram:altsyncram_component|altrom:rom"
Info: Implemented 27 device resources after synthesis - the final resource count might be different
Info: Implemented 11 input pins
Info: Implemented 8 output pins
Info: Implemented 8 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
Info: Processing ended: Sat Jul 23 16:14:57 2005
Info: Elapsed time: 00:00:04
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