datarom.map.talkback.xml

该源码为几个正弦ROM,已经编译并通过,可以直接下载,不需要,内部含有正弦ROM表,还有ROM的宏模块

<!--
This XML file (created on Wed Jul 20 16:45:00 2005) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to www.altera.com/products/software/download/dnl-download_license.html
-->
<talkback>
<ver>5.0</ver>
<schema>quartus_version_5.0_build_148.xsd</schema><license>
	<host_id>00112f2abe5d</host_id>
	<nic_id>00112f2abe5d</nic_id>
	<cdrive_id>90790395</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>5.0</version>
	<build>Build 148</build>
	<module>quartus_map.exe</module>
	<edition>Web Edition</edition>
	<compilation_end_time>Wed Jul 20 16:45:01 2005</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>2</proc_count>
		<cpu_freq units="MHz">2798</cpu_freq>
	</cpu>
	<ram units="MB">512</ram>
</machine>
<top_file>E:/lhh/mokuai/rom/datarom</top_file>
<mep_data>
	<command_line>quartus_map --read_settings_files=on --write_settings_files=off datarom -c datarom</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<messages>
	<warning>Warning: Removed always-enabled tri-state buffer lpm_rom:lpm_rom_component|otri[7] feeding logic, open-drain buffer or output pin</warning>
	<warning>Warning: Removed always-enabled tri-state buffer lpm_rom:lpm_rom_component|otri[6] feeding logic, open-drain buffer or output pin</warning>
	<warning>Warning: Removed always-enabled tri-state buffer lpm_rom:lpm_rom_component|otri[5] feeding logic, open-drain buffer or output pin</warning>
	<warning>Warning: Removed always-enabled tri-state buffer lpm_rom:lpm_rom_component|otri[4] feeding logic, open-drain buffer or output pin</warning>
	<warning>Warning: Removed always-enabled tri-state buffer lpm_rom:lpm_rom_component|otri[3] feeding logic, open-drain buffer or output pin</warning>
	<info>Info: Quartus II Analysis &amp; Synthesis was successful. 0 errors, 8 warnings</info>
	<info>Info: Elapsed time: 00:00:03</info>
	<info>Info: Processing ended: Wed Jul 20 16:45:00 2005</info>
	<info>Info: Implemented 25 device resources after synthesis - the final resource count might be different</info>
	<info>Info: Implemented 8 RAM segments</info>
</messages>
<analysis___synthesis_settings>
	<row>
		<option>Device</option>
		<setting>EP1K30TC144-3</setting>
	</row>
	<row>
		<option>Top-level entity name</option>
		<setting>datarom</setting>
		<default_value>datarom</default_value>
	</row>
	<row>
		<option>Family name</option>
		<setting>ACEX1K</setting>
		<default_value>Stratix</default_value>
	</row>
	<row>
		<option>Use smart compilation</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Create Debugging Nodes for IP Cores</option>
		<setting>off</setting>
		<default_value>off</default_value>
	</row>
	<row>
		<option>Preserve fewer node names</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Disable OpenCore Plus hardware evaluation</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Verilog Version</option>
		<setting>Verilog_2001</setting>
		<default_value>Verilog_2001</default_value>
	</row>
	<row>
		<option>VHDL Version</option>
		<setting>VHDL93</setting>
		<default_value>VHDL93</default_value>
	</row>
	<row>
		<option>State Machine Processing</option>
		<setting>Auto</setting>
		<default_value>Auto</default_value>
	</row>
	<row>
		<option>Extract Verilog State Machines</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Extract VHDL State Machines</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Add Pass-Through Logic to Inferred RAMs</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>NOT Gate Push-Back</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Power-Up Don&apos;t Care</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Remove Redundant Logic Cells</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Remove Duplicate Registers</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Ignore CARRY Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore CASCADE Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore GLOBAL Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore ROW GLOBAL Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore LCELL Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore SOFT Buffers</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Limit AHDL Integers to 32 Bits</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Auto Implement in ROM</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Optimization Technique -- FLEX 10K/10KE/10KA/ACEX 1K</option>
		<setting>Area</setting>
		<default_value>Area</default_value>
	</row>
	<row>
		<option>Carry Chain Length -- FLEX 10K</option>
		<setting>32</setting>
		<default_value>32</default_value>
	</row>
	<row>
		<option>Cascade Chain Length</option>
		<setting>2</setting>
		<default_value>2</default_value>
	</row>
	<row>
		<option>Auto Carry Chains</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Open-Drain Pins</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Remove Duplicate Logic</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto ROM Replacement</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto RAM Replacement</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Clock Enable Replacement</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Resource Sharing</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Allow Any RAM Size For Recognition</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Allow Any ROM Size For Recognition</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore translate_off and translate_on Synthesis Directives</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Show Parameter Settings Tables in Synthesis Report</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
</analysis___synthesis_settings>
<general_register_statistics>
	<row>
		<statistic>Total registers</statistic>
		<value>0</value>
	</row>
	<row>
		<statistic>Number of registers using Synchronous Clear</statistic>
		<value>0</value>
	</row>
	<row>
		<statistic>Number of registers using Synchronous Load</statistic>
		<value>0</value>
	</row>
	<row>
		<statistic>Number of registers using Asynchronous Clear</statistic>
		<value>0</value>
	</row>
	<row>
		<statistic>Number of registers using Asynchronous Load</statistic>
		<value>0</value>
	</row>
	<row>
		<statistic>Number of registers using Clock Enable</statistic>
		<value>0</value>
	</row>
	<row>
		<statistic>Number of registers using Preset</statistic>
		<value>0</value>
	</row>
</general_register_statistics>
<compilation_summary>
	<flow_status>Successful - Wed Jul 20 16:45:00 2005</flow_status>
	<quartus_ii_version>5.0 Build 148 04/26/2005 SJ Web Edition</quartus_ii_version>
	<revision_name>datarom</revision_name>
	<top_level_entity_name>datarom</top_level_entity_name>
	<family>ACEX1K</family>
	<device>EP1K30TC144-3</device>
	<timing_models>Final</timing_models>
	<met_timing_requirements>N/A</met_timing_requirements>
	<total_logic_elements>0</total_logic_elements>
	<total_pins>17</total_pins>
	<total_memory_bits>2,048</total_memory_bits>
	<total_plls>0</total_plls>
</compilation_summary>
<compile_id>3B28E117</compile_id>
</talkback>