sin_rom.tan.talkback.xml

该源码为几个正弦ROM,已经编译并通过,可以直接下载,不需要,内部含有正弦ROM表,还有ROM的宏模块

<!--
This XML file (created on Sat Jul 23 16:15:14 2005) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to www.altera.com/products/software/download/dnl-download_license.html
-->
<talkback>
<ver>5.0</ver>
<schema>quartus_version_5.0_build_148.xsd</schema><license>
	<host_id>00112f2abe5d</host_id>
	<nic_id>00112f2abe5d</nic_id>
	<cdrive_id>90790395</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>5.0</version>
	<build>Build 148</build>
	<module>quartus_tan.exe</module>
	<edition>Web Edition</edition>
	<compilation_end_time>Sat Jul 23 16:15:14 2005</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>2</proc_count>
		<cpu_freq units="MHz">2798</cpu_freq>
	</cpu>
	<ram units="MB">512</ram>
</machine>
<top_file>E:/lhh/mokuai/rom/SIN_ROM</top_file>
<mep_data>
	<command_line>quartus_tan --read_settings_files=off --write_settings_files=off SIN_ROM -c SIN_ROM</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<messages>
	<warning>Warning: Found pins functioning as undefined clocks and/or memory enables</warning>
	<info>Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning</info>
	<info>Info: Elapsed time: 00:00:03</info>
	<info>Info: Processing ended: Sat Jul 23 16:15:14 2005</info>
	<info>Info: th for memory &quot;altsyncram:altsyncram_component|altrom:rom|q[0]~reg_ra4&quot; (data pin = &quot;address[4]&quot;, clock pin = &quot;inclock&quot;) is -0.700 ns</info>
	<info>Info: - Shortest pin to memory delay is 3.600 ns</info>
</messages>
<clock_settings_summary>
	<row>
		<clock_node_name>inclock</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>NONE</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<based_on>NONE</based_on>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
</clock_settings_summary>
<performance>
	<nonclk>
		<type>Worst-case tsu</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>7.500 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case tco</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>18.600 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case th</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>-0.700 ns</actual>
	</nonclk>
</performance>
<compile_id>2C875806</compile_id>
</talkback>