pulse.map.summary

用vhdl实现脉冲宽度可控的一简单程序 仿真环境MAXPLUS-

Flow Status : Successful - Wed Jul 20 17:11:43 2005
Quartus II Version : 4.1 Build 181 06/29/2004 SJ Full Version
Revision Name : pulse
Top-level Entity Name : pulse
Family : Stratix
Total logic elements : 35
Total pins : 14
Total memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0