pulse.fit.qmsg

用vhdl实现脉冲宽度可控的一简单程序 仿真环境MAXPLUS-

{ "Info" "IFYGR_FYGR_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "13 unused 3.30 12 1 0 " "Info: Number of I/O pins in group: 13 (unused VREF, 3.30 VCCIO, 12 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: Details of I/O bank before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 0 29 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  29 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 30 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  30 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 51 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  51 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 1 51 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  51 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use unused 1 28 " "Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  28 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use unused 0 29 " "Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  29 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use unused 0 52 " "Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  52 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use unused 0 51 " "Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  51 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "9 does not use unused 0 6 " "Info: I/O bank number 9 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "10 does not use unused 0 0 " "Info: I/O bank number 10 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "11 does not use unused 0 6 " "Info: I/O bank number 11 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "12 does not use unused 0 0 " "Info: I/O bank number 12 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "after " "Info: Details of I/O bank after I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 0 29 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  29 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 30 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  30 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 51 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  51 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 1 51 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  51 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use unused 13 16 " "Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 13 total pin(s) used --  16 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use unused 0 29 " "Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  29 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use unused 0 52 " "Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  52 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use unused 0 51 " "Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  51 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "9 does not use 3.30V 1 5 " "Info: I/O bank number 9 does not use VREF pins and has 3.30V VCCIO pins. 1 total pin(s) used --  5 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "10 does not use unused 0 0 " "Info: I/O bank number 10 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "11 does not use unused 0 6 " "Info: I/O bank number 11 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "12 does not use unused 0 0 " "Info: I/O bank number 12 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "0 " "Info: Fitter placement preparation operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "1.985 ns register register " "Info: Estimated most critical path is register to register delay of 1.985 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns zz\[2\] 1 REG LAB_X31_Y28 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X31_Y28; Fanout = 4; REG Node = 'zz\[2\]'" {  } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "" { zz[2] } "NODE_NAME" } } } { "D:/MD/vhd/alter/pulse_change/pulse.vhd" "" "" { Text "D:/MD/vhd/alter/pulse_change/pulse.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.241 ns) + CELL(0.366 ns) 0.607 ns add~47 2 COMB LAB_X30_Y28 2 " "Info: 2: + IC(0.241 ns) + CELL(0.366 ns) = 0.607 ns; Loc. = LAB_X30_Y28; Fanout = 2; COMB Node = 'add~47'" {  } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "0.607 ns" { zz[2] add~47 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.227 ns) + CELL(0.183 ns) 1.017 ns add~61 3 COMB LAB_X30_Y28 2 " "Info: 3: + IC(0.227 ns) + CELL(0.183 ns) = 1.017 ns; Loc. = LAB_X30_Y28; Fanout = 2; COMB Node = 'add~61'" {  } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "0.410 ns" { add~47 add~61 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.227 ns) + CELL(0.183 ns) 1.427 ns reduce_nor~2 4 COMB LAB_X30_Y28 2 " "Info: 4: + IC(0.227 ns) + CELL(0.183 ns) = 1.427 ns; Loc. = LAB_X30_Y28; Fanout = 2; COMB Node = 'reduce_nor~2'" {  } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "0.410 ns" { add~61 reduce_nor~2 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.335 ns) + CELL(0.223 ns) 1.985 ns b 5 REG LAB_X30_Y28 10 " "Info: 5: + IC(0.335 ns) + CELL(0.223 ns) = 1.985 ns; Loc. = LAB_X30_Y28; Fanout = 10; REG Node = 'b'" {  } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "0.558 ns" { reduce_nor~2 b } "NODE_NAME" } } } { "D:/MD/vhd/alter/pulse_change/pulse.vhd" "" "" { Text "D:/MD/vhd/alter/pulse_change/pulse.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.955 ns 48.11 % " "Info: Total cell delay = 0.955 ns ( 48.11 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.030 ns 51.89 % " "Info: Total interconnect delay = 1.030 ns ( 51.89 % )" {  } {  } 0}  } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "1.985 ns" { zz[2] add~47 add~61 reduce_nor~2 b } "NODE_NAME" } } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PLACER_ESTIMATED_PERCENT_ROUTING_RESOURCE_USAGE" "1 " "Info: Estimated interconnect usage is 1% of the available device resources" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "0 " "Info: Fitter placement operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "0 " "Info: Fitter routing operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 20 17:12:08 2005 " "Info: Processing ended: Wed Jul 20 17:12:08 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:24 " "Info: Elapsed time: 00:00:24" {  } {  } 0}  } {  } 0}