pulse.hif

用vhdl实现脉冲宽度可控的一简单程序 仿真环境MAXPLUS-

Version 4.1 Build 181 06/29/2004 SJ Full Version
34
OFF
OFF
OFF
OFF
0
# entity
pulse
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
pulse.vhd
1121850698
4
# storage
db|pulse.(0).cnf
db|pulse.(0).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# complete