pulse.tan.qmsg

用vhdl实现脉冲宽度可控的一简单程序 仿真环境MAXPLUS-

{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk q q~reg0 6.801 ns register " "Info: Minimum tco from clock clk to destination pin q through register q~reg0 is 6.801 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.787 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 2.787 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 9 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 9; CLK Node = 'clk'" {  } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/MD/vhd/alter/pulse_change/pulse.vhd" "" "" { Text "D:/MD/vhd/alter/pulse_change/pulse.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.520 ns) + CELL(0.542 ns) 2.787 ns q~reg0 2 REG LC_X31_Y28_N9 1 " "Info: 2: + IC(1.520 ns) + CELL(0.542 ns) = 2.787 ns; Loc. = LC_X31_Y28_N9; Fanout = 1; REG Node = 'q~reg0'" {  } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "2.062 ns" { clk q~reg0 } "NODE_NAME" } } } { "D:/MD/vhd/alter/pulse_change/pulse.vhd" "" "" { Text "D:/MD/vhd/alter/pulse_change/pulse.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 45.46 % " "Info: Total cell delay = 1.267 ns ( 45.46 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.520 ns 54.54 % " "Info: Total interconnect delay = 1.520 ns ( 54.54 % )" {  } {  } 0}  } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "2.787 ns" { clk q~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "D:/MD/vhd/alter/pulse_change/pulse.vhd" "" "" { Text "D:/MD/vhd/alter/pulse_change/pulse.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.858 ns + Shortest register pin " "Info: + Shortest register to pin delay is 3.858 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q~reg0 1 REG LC_X31_Y28_N9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X31_Y28_N9; Fanout = 1; REG Node = 'q~reg0'" {  } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "" { q~reg0 } "NODE_NAME" } } } { "D:/MD/vhd/alter/pulse_change/pulse.vhd" "" "" { Text "D:/MD/vhd/alter/pulse_change/pulse.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.454 ns) + CELL(2.404 ns) 3.858 ns q 2 PIN PIN_L7 0 " "Info: 2: + IC(1.454 ns) + CELL(2.404 ns) = 3.858 ns; Loc. = PIN_L7; Fanout = 0; PIN Node = 'q'" {  } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "3.858 ns" { q~reg0 q } "NODE_NAME" } } } { "D:/MD/vhd/alter/pulse_change/pulse.vhd" "" "" { Text "D:/MD/vhd/alter/pulse_change/pulse.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.404 ns 62.31 % " "Info: Total cell delay = 2.404 ns ( 62.31 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.454 ns 37.69 % " "Info: Total interconnect delay = 1.454 ns ( 37.69 % )" {  } {  } 0}  } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "3.858 ns" { q~reg0 q } "NODE_NAME" } } }  } 0}  } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "2.787 ns" { clk q~reg0 } "NODE_NAME" } } } { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "3.858 ns" { q~reg0 q } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 20 17:12:17 2005 " "Info: Processing ended: Wed Jul 20 17:12:17 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}