📄 pulse.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register zz\[2\] register a 419.99 MHz 2.381 ns Internal " "Info: Clock clk has Internal fmax of 419.99 MHz between source register zz\[2\] and destination register a (period= 2.381 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.215 ns + Longest register register " "Info: + Longest register to register delay is 2.215 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns zz\[2\] 1 REG LC_X31_Y28_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X31_Y28_N2; Fanout = 4; REG Node = 'zz\[2\]'" { } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "" { zz[2] } "NODE_NAME" } } } { "D:/MD/vhd/alter/pulse_change/pulse.vhd" "" "" { Text "D:/MD/vhd/alter/pulse_change/pulse.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.546 ns) + CELL(0.280 ns) 0.826 ns add~47 2 COMB LC_X30_Y28_N6 2 " "Info: 2: + IC(0.546 ns) + CELL(0.280 ns) = 0.826 ns; Loc. = LC_X30_Y28_N6; Fanout = 2; COMB Node = 'add~47'" { } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "0.826 ns" { zz[2] add~47 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.315 ns) + CELL(0.075 ns) 1.216 ns add~61 3 COMB LC_X30_Y28_N8 2 " "Info: 3: + IC(0.315 ns) + CELL(0.075 ns) = 1.216 ns; Loc. = LC_X30_Y28_N8; Fanout = 2; COMB Node = 'add~61'" { } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "0.390 ns" { add~47 add~61 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.348 ns) + CELL(0.075 ns) 1.639 ns reduce_nor~2 4 COMB LC_X30_Y28_N0 2 " "Info: 4: + IC(0.348 ns) + CELL(0.075 ns) = 1.639 ns; Loc. = LC_X30_Y28_N0; Fanout = 2; COMB Node = 'reduce_nor~2'" { } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "0.423 ns" { add~61 reduce_nor~2 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.491 ns) + CELL(0.085 ns) 2.215 ns a 5 REG LC_X30_Y28_N5 10 " "Info: 5: + IC(0.491 ns) + CELL(0.085 ns) = 2.215 ns; Loc. = LC_X30_Y28_N5; Fanout = 10; REG Node = 'a'" { } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "0.576 ns" { reduce_nor~2 a } "NODE_NAME" } } } { "D:/MD/vhd/alter/pulse_change/pulse.vhd" "" "" { Text "D:/MD/vhd/alter/pulse_change/pulse.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.515 ns 23.25 % " "Info: Total cell delay = 0.515 ns ( 23.25 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.700 ns 76.75 % " "Info: Total interconnect delay = 1.700 ns ( 76.75 % )" { } { } 0} } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "2.215 ns" { zz[2] add~47 add~61 reduce_nor~2 a } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.787 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 2.787 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 9 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 9; CLK Node = 'clk'" { } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/MD/vhd/alter/pulse_change/pulse.vhd" "" "" { Text "D:/MD/vhd/alter/pulse_change/pulse.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.520 ns) + CELL(0.542 ns) 2.787 ns a 2 REG LC_X30_Y28_N5 10 " "Info: 2: + IC(1.520 ns) + CELL(0.542 ns) = 2.787 ns; Loc. = LC_X30_Y28_N5; Fanout = 10; REG Node = 'a'" { } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "2.062 ns" { clk a } "NODE_NAME" } } } { "D:/MD/vhd/alter/pulse_change/pulse.vhd" "" "" { Text "D:/MD/vhd/alter/pulse_change/pulse.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 45.46 % " "Info: Total cell delay = 1.267 ns ( 45.46 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.520 ns 54.54 % " "Info: Total interconnect delay = 1.520 ns ( 54.54 % )" { } { } 0} } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "2.787 ns" { clk a } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.787 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 2.787 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 9 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 9; CLK Node = 'clk'" { } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/MD/vhd/alter/pulse_change/pulse.vhd" "" "" { Text "D:/MD/vhd/alter/pulse_change/pulse.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.520 ns) + CELL(0.542 ns) 2.787 ns zz\[2\] 2 REG LC_X31_Y28_N2 4 " "Info: 2: + IC(1.520 ns) + CELL(0.542 ns) = 2.787 ns; Loc. = LC_X31_Y28_N2; Fanout = 4; REG Node = 'zz\[2\]'" { } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "2.062 ns" { clk zz[2] } "NODE_NAME" } } } { "D:/MD/vhd/alter/pulse_change/pulse.vhd" "" "" { Text "D:/MD/vhd/alter/pulse_change/pulse.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 45.46 % " "Info: Total cell delay = 1.267 ns ( 45.46 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.520 ns 54.54 % " "Info: Total interconnect delay = 1.520 ns ( 54.54 % )" { } { } 0} } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "2.787 ns" { clk zz[2] } "NODE_NAME" } } } } 0} } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "2.787 ns" { clk a } "NODE_NAME" } } } { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "2.787 ns" { clk zz[2] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" { } { { "D:/MD/vhd/alter/pulse_change/pulse.vhd" "" "" { Text "D:/MD/vhd/alter/pulse_change/pulse.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "D:/MD/vhd/alter/pulse_change/pulse.vhd" "" "" { Text "D:/MD/vhd/alter/pulse_change/pulse.vhd" 15 -1 0 } } } 0} } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "2.215 ns" { zz[2] add~47 add~61 reduce_nor~2 a } "NODE_NAME" } } } { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "2.787 ns" { clk a } "NODE_NAME" } } } { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "2.787 ns" { clk zz[2] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "b z\[3\] clk 5.986 ns register " "Info: tsu for register b (data pin = z\[3\], clock pin = clk) is 5.986 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.763 ns + Longest pin register " "Info: + Longest pin to register delay is 8.763 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns z\[3\] 1 PIN PIN_J8 4 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_J8; Fanout = 4; PIN Node = 'z\[3\]'" { } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "" { z[3] } "NODE_NAME" } } } { "D:/MD/vhd/alter/pulse_change/pulse.vhd" "" "" { Text "D:/MD/vhd/alter/pulse_change/pulse.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.065 ns) + CELL(0.366 ns) 5.518 ns reduce_nor~97 2 COMB LC_X29_Y28_N3 1 " "Info: 2: + IC(4.065 ns) + CELL(0.366 ns) = 5.518 ns; Loc. = LC_X29_Y28_N3; Fanout = 1; COMB Node = 'reduce_nor~97'" { } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "4.431 ns" { z[3] reduce_nor~97 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.890 ns) + CELL(0.280 ns) 6.688 ns reduce_nor~0 3 COMB LC_X30_Y29_N6 2 " "Info: 3: + IC(0.890 ns) + CELL(0.280 ns) = 6.688 ns; Loc. = LC_X30_Y29_N6; Fanout = 2; COMB Node = 'reduce_nor~0'" { } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "1.170 ns" { reduce_nor~97 reduce_nor~0 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.975 ns) + CELL(0.280 ns) 7.943 ns b~177 4 COMB LC_X31_Y28_N7 1 " "Info: 4: + IC(0.975 ns) + CELL(0.280 ns) = 7.943 ns; Loc. = LC_X31_Y28_N7; Fanout = 1; COMB Node = 'b~177'" { } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "1.255 ns" { reduce_nor~0 b~177 } "NODE_NAME" } } } { "D:/MD/vhd/alter/pulse_change/pulse.vhd" "" "" { Text "D:/MD/vhd/alter/pulse_change/pulse.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.501 ns) + CELL(0.319 ns) 8.763 ns b 5 REG LC_X30_Y28_N1 10 " "Info: 5: + IC(0.501 ns) + CELL(0.319 ns) = 8.763 ns; Loc. = LC_X30_Y28_N1; Fanout = 10; REG Node = 'b'" { } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "0.820 ns" { b~177 b } "NODE_NAME" } } } { "D:/MD/vhd/alter/pulse_change/pulse.vhd" "" "" { Text "D:/MD/vhd/alter/pulse_change/pulse.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.332 ns 26.61 % " "Info: Total cell delay = 2.332 ns ( 26.61 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.431 ns 73.39 % " "Info: Total interconnect delay = 6.431 ns ( 73.39 % )" { } { } 0} } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "8.763 ns" { z[3] reduce_nor~97 reduce_nor~0 b~177 b } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "D:/MD/vhd/alter/pulse_change/pulse.vhd" "" "" { Text "D:/MD/vhd/alter/pulse_change/pulse.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.787 ns - Shortest register " "Info: - Shortest clock path from clock clk to destination register is 2.787 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 9 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 9; CLK Node = 'clk'" { } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/MD/vhd/alter/pulse_change/pulse.vhd" "" "" { Text "D:/MD/vhd/alter/pulse_change/pulse.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.520 ns) + CELL(0.542 ns) 2.787 ns b 2 REG LC_X30_Y28_N1 10 " "Info: 2: + IC(1.520 ns) + CELL(0.542 ns) = 2.787 ns; Loc. = LC_X30_Y28_N1; Fanout = 10; REG Node = 'b'" { } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "2.062 ns" { clk b } "NODE_NAME" } } } { "D:/MD/vhd/alter/pulse_change/pulse.vhd" "" "" { Text "D:/MD/vhd/alter/pulse_change/pulse.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 45.46 % " "Info: Total cell delay = 1.267 ns ( 45.46 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.520 ns 54.54 % " "Info: Total interconnect delay = 1.520 ns ( 54.54 % )" { } { } 0} } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "2.787 ns" { clk b } "NODE_NAME" } } } } 0} } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "8.763 ns" { z[3] reduce_nor~97 reduce_nor~0 b~177 b } "NODE_NAME" } } } { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "2.787 ns" { clk b } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk q q~reg0 6.801 ns register " "Info: tco from clock clk to destination pin q through register q~reg0 is 6.801 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.787 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 2.787 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 9 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 9; CLK Node = 'clk'" { } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/MD/vhd/alter/pulse_change/pulse.vhd" "" "" { Text "D:/MD/vhd/alter/pulse_change/pulse.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.520 ns) + CELL(0.542 ns) 2.787 ns q~reg0 2 REG LC_X31_Y28_N9 1 " "Info: 2: + IC(1.520 ns) + CELL(0.542 ns) = 2.787 ns; Loc. = LC_X31_Y28_N9; Fanout = 1; REG Node = 'q~reg0'" { } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "2.062 ns" { clk q~reg0 } "NODE_NAME" } } } { "D:/MD/vhd/alter/pulse_change/pulse.vhd" "" "" { Text "D:/MD/vhd/alter/pulse_change/pulse.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 45.46 % " "Info: Total cell delay = 1.267 ns ( 45.46 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.520 ns 54.54 % " "Info: Total interconnect delay = 1.520 ns ( 54.54 % )" { } { } 0} } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "2.787 ns" { clk q~reg0 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" { } { { "D:/MD/vhd/alter/pulse_change/pulse.vhd" "" "" { Text "D:/MD/vhd/alter/pulse_change/pulse.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.858 ns + Longest register pin " "Info: + Longest register to pin delay is 3.858 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q~reg0 1 REG LC_X31_Y28_N9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X31_Y28_N9; Fanout = 1; REG Node = 'q~reg0'" { } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "" { q~reg0 } "NODE_NAME" } } } { "D:/MD/vhd/alter/pulse_change/pulse.vhd" "" "" { Text "D:/MD/vhd/alter/pulse_change/pulse.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.454 ns) + CELL(2.404 ns) 3.858 ns q 2 PIN PIN_L7 0 " "Info: 2: + IC(1.454 ns) + CELL(2.404 ns) = 3.858 ns; Loc. = PIN_L7; Fanout = 0; PIN Node = 'q'" { } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "3.858 ns" { q~reg0 q } "NODE_NAME" } } } { "D:/MD/vhd/alter/pulse_change/pulse.vhd" "" "" { Text "D:/MD/vhd/alter/pulse_change/pulse.vhd" 7 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.404 ns 62.31 % " "Info: Total cell delay = 2.404 ns ( 62.31 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.454 ns 37.69 % " "Info: Total interconnect delay = 1.454 ns ( 37.69 % )" { } { } 0} } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "3.858 ns" { q~reg0 q } "NODE_NAME" } } } } 0} } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "2.787 ns" { clk q~reg0 } "NODE_NAME" } } } { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "3.858 ns" { q~reg0 q } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_TH_RESULT" "zz\[2\] z\[2\] clk -2.660 ns register " "Info: th for register zz\[2\] (data pin = z\[2\], clock pin = clk) is -2.660 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.787 ns + Longest register " "Info: + Longest clock path from clock clk to destination register is 2.787 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 9 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 9; CLK Node = 'clk'" { } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/MD/vhd/alter/pulse_change/pulse.vhd" "" "" { Text "D:/MD/vhd/alter/pulse_change/pulse.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.520 ns) + CELL(0.542 ns) 2.787 ns zz\[2\] 2 REG LC_X31_Y28_N2 4 " "Info: 2: + IC(1.520 ns) + CELL(0.542 ns) = 2.787 ns; Loc. = LC_X31_Y28_N2; Fanout = 4; REG Node = 'zz\[2\]'" { } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "2.062 ns" { clk zz[2] } "NODE_NAME" } } } { "D:/MD/vhd/alter/pulse_change/pulse.vhd" "" "" { Text "D:/MD/vhd/alter/pulse_change/pulse.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 45.46 % " "Info: Total cell delay = 1.267 ns ( 45.46 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.520 ns 54.54 % " "Info: Total interconnect delay = 1.520 ns ( 54.54 % )" { } { } 0} } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "2.787 ns" { clk zz[2] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" { } { { "D:/MD/vhd/alter/pulse_change/pulse.vhd" "" "" { Text "D:/MD/vhd/alter/pulse_change/pulse.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.547 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.547 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns z\[2\] 1 PIN PIN_G9 4 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_G9; Fanout = 4; PIN Node = 'z\[2\]'" { } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "" { z[2] } "NODE_NAME" } } } { "D:/MD/vhd/alter/pulse_change/pulse.vhd" "" "" { Text "D:/MD/vhd/alter/pulse_change/pulse.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.836 ns) + CELL(0.075 ns) 4.998 ns add~16 2 COMB LC_X31_Y28_N4 1 " "Info: 2: + IC(3.836 ns) + CELL(0.075 ns) = 4.998 ns; Loc. = LC_X31_Y28_N4; Fanout = 1; COMB Node = 'add~16'" { } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "3.911 ns" { z[2] add~16 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.326 ns) + CELL(0.223 ns) 5.547 ns zz\[2\] 3 REG LC_X31_Y28_N2 4 " "Info: 3: + IC(0.326 ns) + CELL(0.223 ns) = 5.547 ns; Loc. = LC_X31_Y28_N2; Fanout = 4; REG Node = 'zz\[2\]'" { } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "0.549 ns" { add~16 zz[2] } "NODE_NAME" } } } { "D:/MD/vhd/alter/pulse_change/pulse.vhd" "" "" { Text "D:/MD/vhd/alter/pulse_change/pulse.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.385 ns 24.97 % " "Info: Total cell delay = 1.385 ns ( 24.97 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.162 ns 75.03 % " "Info: Total interconnect delay = 4.162 ns ( 75.03 % )" { } { } 0} } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "5.547 ns" { z[2] add~16 zz[2] } "NODE_NAME" } } } } 0} } { { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "2.787 ns" { clk zz[2] } "NODE_NAME" } } } { "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" "" "" { Report "D:/MD/vhd/alter/pulse_change/db/pulse_cmp.qrpt" Compiler "pulse" "UNKNOWN" "V1" "D:/MD/vhd/alter/pulse_change/db/pulse.quartus_db" { Floorplan "" "" "5.547 ns" { z[2] add~16 zz[2] } "NODE_NAME" } } } } 0}
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