pulse.map.qmsg

用vhdl实现脉冲宽度可控的一简单程序 仿真环境MAXPLUS-

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jul 20 17:11:41 2005 " "Info: Processing started: Wed Jul 20 17:11:41 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off pulse -c pulse " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off pulse -c pulse" {  } {  } 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "D:/MD/vhd/alter/pulse_change/pulse.tdf " "Warning: Can't analyze file -- file D:/MD/vhd/alter/pulse_change/pulse.tdf is missing" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pulse.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file pulse.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pulse-rtl " "Info: Found design unit 1: pulse-rtl" {  } { { "D:/MD/vhd/alter/pulse_change/pulse.vhd" "pulse-rtl" "" { Text "D:/MD/vhd/alter/pulse_change/pulse.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 pulse " "Info: Found entity 1: pulse" {  } { { "D:/MD/vhd/alter/pulse_change/pulse.vhd" "pulse" "" { Text "D:/MD/vhd/alter/pulse_change/pulse.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "D:/MD/vhd/alter/pulse_change_1/pulse_1.tdf " "Warning: Can't analyze file -- file D:/MD/vhd/alter/pulse_change_1/pulse_1.tdf is missing" {  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "49 " "Info: Implemented 49 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "13 " "Info: Implemented 13 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "35 " "Info: Implemented 35 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 20 17:11:43 2005 " "Info: Processing ended: Wed Jul 20 17:11:43 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}