pulse.fit.summary

用vhdl实现脉冲宽度可控的一简单程序 仿真环境MAXPLUS-

Flow Status : Successful - Wed Jul 20 17:12:08 2005
Quartus II Version : 4.1 Build 181 06/29/2004 SJ Full Version
Revision Name : pulse
Top-level Entity Name : pulse
Family : Stratix
Total logic elements : 35 / 10,570 ( < 1 % )
Total pins : 14 / 336 ( 4 % )
Total memory bits : 0 / 920,448 ( 0 % )
DSP block 9-bit elements : 0 / 48 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )
Device : EP1S10F484C5
Timing Models : Production