pulse.fit.eqn

用vhdl实现脉冲宽度可控的一简单程序 仿真环境MAXPLUS-

--A1L13Q is q~reg0 at LC_X31_Y28_N9
--operation mode is normal

A1L13Q_lut_out = !b;
A1L13Q = DFFEA(A1L13Q_lut_out, GLOBAL(clk), VCC, , !a, , );


--b is b at LC_X30_Y28_N1
--operation mode is normal

b_lut_out = A1L12 # a & (b $ !A1L43);
b = DFFEA(b_lut_out, GLOBAL(clk), VCC, , , , );


--a is a at LC_X30_Y28_N5
--operation mode is normal

a_lut_out = A1L23 & (A1L33 # !b) # !A1L23 & b & A1L33;
a_sload_eqn = (a & A1L43) # (!a & a_lut_out);
a = DFFEA(a_sload_eqn, GLOBAL(clk), VCC, , , , );


--A1L53 is reduce_nor~96 at LC_X29_Y28_N1
--operation mode is normal

A1L53 = f[2] # f[3] # f[0] $ !f[1];


--A1L61 is add~77 at LC_X29_Y28_N0
--operation mode is normal

A1L61 = f[2] # f[1] # f[0];


--A1L91 is add~91 at LC_X29_Y28_N2
--operation mode is normal

A1L91 = f[5] $ (A1L61 # f[4] # f[3]);


--A1L81 is add~86 at LC_X29_Y28_N6
--operation mode is normal

A1L81 = f[4] $ (A1L61 # f[3]);


--A1L33 is reduce_nor~1 at LC_X29_Y28_N5
--operation mode is normal

A1L33 = A1L53 # !f[0] # !A1L81 # !A1L91;


--A1L63 is reduce_nor~97 at LC_X29_Y28_N3
--operation mode is normal

A1L63 = z[3] # z[2] # z[0] $ !z[1];


--A1L4 is add~17 at LC_X30_Y29_N4
--operation mode is normal

A1L4 = z[2] # z[1] # z[0];


--A1L7 is add~31 at LC_X30_Y29_N5
--operation mode is normal

A1L7 = z[5] $ (A1L4 # z[4] # z[3]);


--A1L6 is add~26 at LC_X30_Y29_N2
--operation mode is normal

A1L6 = z[4] $ (A1L4 # z[3]);


--A1L23 is reduce_nor~0 at LC_X30_Y29_N6
--operation mode is normal

A1L23 = A1L63 # !A1L6 # !A1L7 # !z[0];


--A1L12 is b~177 at LC_X31_Y28_N7
--operation mode is normal

A1L12 = !a & (b & A1L33 # !b & !A1L23);


--zz[3] is zz[3] at LC_X31_Y28_N0
--operation mode is normal

zz[3]_lut_out = b & !A1L71 # !b & !A1L5;
zz[3]_sload_eqn = (a & A1L11) # (!a & zz[3]_lut_out);
zz[3] = DFFEA(zz[3]_sload_eqn, GLOBAL(clk), VCC, , , , );


--zz[2] is zz[2] at LC_X31_Y28_N2
--operation mode is normal

zz[2]_lut_out = b & !A1L51 # !b & !A1L3;
zz[2]_sload_eqn = (a & A1L9) # (!a & zz[2]_lut_out);
zz[2] = DFFEA(zz[2]_sload_eqn, GLOBAL(clk), VCC, , , , );


--zz[1] is zz[1] at LC_X31_Y28_N6
--operation mode is normal

zz[1]_lut_out = A1L2 & !A1L41 & b # !A1L2 & (!b # !A1L41);
zz[1]_sload_eqn = (a & A1L8) # (!a & zz[1]_lut_out);
zz[1] = DFFEA(zz[1]_sload_eqn, GLOBAL(clk), VCC, , , , );


--zz[0] is zz[0] at LC_X30_Y28_N2
--operation mode is normal

zz[0]_lut_out = zz[0] & !a & !A1L25 # !zz[0] & (a # !A1L25);
zz[0] = DFFEA(zz[0]_lut_out, GLOBAL(clk), VCC, , , , );


--A1L73 is reduce_nor~98 at LC_X30_Y28_N9
--operation mode is normal

A1L73 = zz[3] # zz[2] # zz[0] $ !zz[1];


--zz[4] is zz[4] at LC_X30_Y28_N4
--operation mode is normal

zz[4]_lut_out = A1L6 & b & !A1L81 # !A1L6 & (!A1L81 # !b);
zz[4]_sload_eqn = (a & A1L21) # (!a & zz[4]_lut_out);
zz[4] = DFFEA(zz[4]_sload_eqn, GLOBAL(clk), VCC, , , , );


--A1L01 is add~47 at LC_X30_Y28_N6
--operation mode is normal

A1L01 = zz[2] # zz[1] # zz[0];


--zz[5] is zz[5] at LC_X30_Y28_N3
--operation mode is normal

zz[5]_lut_out = A1L7 & b & !A1L91 # !A1L7 & (!A1L91 # !b);
zz[5]_sload_eqn = (a & A1L31) # (!a & zz[5]_lut_out);
zz[5] = DFFEA(zz[5]_sload_eqn, GLOBAL(clk), VCC, , , , );


--A1L31 is add~61 at LC_X30_Y28_N8
--operation mode is normal

A1L31 = zz[5] $ (!zz[4] & !zz[3] & !A1L01);


--A1L21 is add~56 at LC_X30_Y28_N7
--operation mode is normal

A1L21 = zz[4] $ (!zz[3] & !A1L01);


--A1L43 is reduce_nor~2 at LC_X30_Y28_N0
--operation mode is normal

A1L43 = A1L73 # A1L21 # A1L31 # !zz[0];


--A1L5 is add~21 at LC_X31_Y28_N8
--operation mode is normal

A1L5 = z[3] $ (z[1] # z[0] # z[2]);


--A1L71 is add~81 at LC_X29_Y28_N8
--operation mode is normal

A1L71 = f[3] $ (f[0] # f[2] # f[1]);


--A1L11 is add~51 at LC_X31_Y28_N5
--operation mode is normal

A1L11 = zz[3] $ (!zz[2] & !zz[1] & !zz[0]);


--A1L3 is add~16 at LC_X31_Y28_N4
--operation mode is normal

A1L3 = z[2] $ (z[1] # z[0]);


--A1L51 is add~76 at LC_X29_Y28_N9
--operation mode is normal

A1L51 = f[2] $ (f[1] # f[0]);


--A1L9 is add~46 at LC_X31_Y28_N1
--operation mode is normal

A1L9 = zz[2] $ (!zz[1] & !zz[0]);


--A1L2 is add~11 at LC_X30_Y29_N9
--operation mode is normal

A1L2 = z[1] $ z[0];


--A1L41 is add~71 at LC_X29_Y28_N7
--operation mode is normal

A1L41 = f[1] $ f[0];


--A1L8 is add~41 at LC_X31_Y28_N3
--operation mode is normal

A1L8 = zz[1] $ !zz[0];


--A1L25 is zz~164 at LC_X29_Y28_N4
--operation mode is normal

A1L25 = f[0] & (z[0] # b) # !f[0] & z[0] & !b;


--clk is clk at PIN_L2
--operation mode is input

clk = INPUT();


--f[2] is f[2] at PIN_B11
--operation mode is input

f[2] = INPUT();


--f[3] is f[3] at PIN_C12
--operation mode is input

f[3] = INPUT();


--f[0] is f[0] at PIN_D12
--operation mode is input

f[0] = INPUT();


--f[1] is f[1] at PIN_K8
--operation mode is input

f[1] = INPUT();


--f[4] is f[4] at PIN_C13
--operation mode is input

f[4] = INPUT();


--f[5] is f[5] at PIN_A11
--operation mode is input

f[5] = INPUT();


--z[2] is z[2] at PIN_G9
--operation mode is input

z[2] = INPUT();


--z[3] is z[3] at PIN_J8
--operation mode is input

z[3] = INPUT();


--z[0] is z[0] at PIN_F10
--operation mode is input

z[0] = INPUT();


--z[1] is z[1] at PIN_K10
--operation mode is input

z[1] = INPUT();


--z[4] is z[4] at PIN_H10
--operation mode is input

z[4] = INPUT();


--z[5] is z[5] at PIN_J9
--operation mode is input

z[5] = INPUT();


--q is q at PIN_L7
--operation mode is output

q = OUTPUT(A1L13Q);