time.map.summary

用vhdl实现24小时计数器

Flow Status : Successful - Sun Mar 13 23:18:26 2005
Quartus II Version : 4.1 Build 181 06/29/2004 SJ Full Version
Revision Name : time
Top-level Entity Name : time
Family : Stratix
Total logic elements : 16
Total pins : 10
Total memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0