📄 xr16.md
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reg: SUBU4(reg,reg) "subl r%c,r%0,r%1\n" 1
reg: ADDI2(reg,con) "addi r%c,r%0,%1\n" 1
reg: ADDI4(reg,con) "addil r%c,r%0,%1\n" 1
reg: ADDP2(reg,con) "addi r%c,r%0,%1\n" 1
reg: ADDU2(reg,con) "addi r%c,r%0,%1\n" 1
reg: ADDU4(reg,con) "addil r%c,r%0,%1\n" 1
reg: BANDI2(reg,con) "?mov r%c,r%0\nandi r%c,%1\n" 1
reg: BANDI4(reg,con) "?movl r%c,r%0\nandil r%c,%1\n" 1
reg: BORI2(reg,con) "?mov r%c,r%0\nori r%c,%1\n" 1
reg: BORI4(reg,con) "?movl r%c,r%0\noril r%c,%1\n" 1
reg: BXORI2(reg,con) "?mov r%c,r%0\nxori r%c,%1\n" 1
reg: BXORI4(reg,con) "?movl r%c,r%0\nxoril r%c,%1\n" 1
reg: BANDU2(reg,con) "?mov r%c,r%0\nandi r%c,%1\n" 1
reg: BANDU4(reg,con) "?movl r%c,r%0\nandil r%c,%1\n" 1
reg: BORU2(reg,con) "?mov r%c,r%0\nori r%c,%1\n" 1
reg: BORU4(reg,con) "?movl r%c,r%0\noril r%c,%1\n" 1
reg: BXORU2(reg,con) "?mov r%c,r%0\nxori r%c,%1\n" 1
reg: BXORU4(reg,con) "?movl r%c,r%0\nxoril r%c,%1\n" 1
reg: SUBI2(reg,con) "subi r%c,r%0,%1\n" 1
reg: SUBI4(reg,con) "subil r%c,r%0,%1\n" 1
reg: SUBP2(reg,con) "subi r%c,r%0,%1\n" 1
reg: SUBU2(reg,con) "subi r%c,r%0,%1\n" 1
reg: SUBU4(reg,con) "subil r%c,r%0,%1\n" 1
reg: LSHI2(reg,reg) "call _sllr\n" 10
reg: LSHI4(reg,reg) "call _slllr\n" 10
reg: LSHU2(reg,reg) "call _sllr\n" 10
reg: LSHU4(reg,reg) "call _slllr\n" 10
reg: RSHI2(reg,reg) "call _srar\n" 10
reg: RSHI4(reg,reg) "call _sralr\n" 10
reg: RSHU2(reg,reg) "call _srlr\n" 10
reg: RSHU4(reg,reg) "call _srllr\n" 10
reg: LSHI2(reg,con) "?mov r%c,r%0\nslli r%c,%1\n" 1
reg: LSHI4(reg,con) "?movl r%c,r%0\nsllil r%c,%1\n" 1
reg: LSHU2(reg,con) "?mov r%c,r%0\nslli r%c,%1\n" 1
reg: LSHU4(reg,con) "?movl r%c,r%0\nsllil r%c,%1\n" 1
reg: RSHI2(reg,con) "?mov r%c,r%0\nsrai r%c,%1\n" 1
reg: RSHI4(reg,con) "?movl r%c,r%0\nsrail r%c,%1\n" 1
reg: RSHU2(reg,con) "?mov r%c,r%0\nsrli r%c,%1\n" 1
reg: RSHU4(reg,con) "?movl r%c,r%0\nsrlil r%c,%1\n" 1
reg: BCOMI2(reg) "?mov r%c,r%0\nxori r%c,-1\n" 1
reg: BCOMI4(reg) "?movl r%c,r%0\nxoril r%c,-1\n" 1
reg: BCOMU2(reg) "?mov r%c,r%0\nxori r%c,-1\n" 1
reg: BCOMU4(reg) "?movl r%c,r%0\nxoril r%c,-1\n" 1
reg: NEGI2(reg) "sub r%c,r0,r%0\n" 1
reg: NEGI4(reg) "subl r%c,r0,r%0\n" 1
reg: LOADI1(reg) "mov r%c,r%0\n" move(a)
reg: LOADU1(reg) "mov r%c,r%0\n" move(a)
reg: LOADI2(reg) "mov r%c,r%0\n" move(a)
reg: LOADU2(reg) "mov r%c,r%0\n" move(a)
reg: LOADI4(reg) "mov r%c,r%0\n" move(a)
reg: LOADP2(reg) "mov r%c,r%0\n" move(a)
reg: LOADU4(reg) "mov r%c,r%0\n" move(a)
reg: ADDF4(reg,reg) "" fp()
reg: DIVF4(reg,reg) "" fp()
reg: MULF4(reg,reg) "" fp()
reg: SUBF4(reg,reg) "" fp()
reg: LOADF4(reg) "" move(a)+fp()
reg: NEGF4(reg) "" fp()
reg: CVII2(reg) "sext r%c,r%0\n" 1
reg: CVUI2(reg) "zext r%c,r%0\n" 1
reg: CVUU2(reg) "zext r%c,r%0\n" 1
reg: CVII4(reg) "sexl r%c,r%0\n" 1
reg: CVIU4(reg) "sexl r%c,r%0\n" 1
reg: CVUI4(reg) "zexl r%c,r%0\n" 1
reg: CVUU4(reg) "zexl r%c,r%0\n" 1
reg: CVFF4(reg) "" fp()
reg: CVIF4(reg) "" fp()
reg: CVFI2(reg) "" fp()
reg: CVFI4(reg) "" fp()
stmt: LABELV "%a:\n"
stmt: JUMPV(acon) "br %0\n" 1
stmt: JUMPV(reg) "jal r0,0(r%0)\n" 1
stmt: EQI2(reg,reg) "cmp r%0,r%1\nbeq %a\n" 2
stmt: EQI4(reg,reg) "cmpl r%0,r%1\nbeq %a\n" 2
stmt: EQU2(reg,reg) "cmp r%0,r%1\nbeq %a\n" 2
stmt: EQU4(reg,reg) "cmpl r%0,r%1\nbeq %a\n" 2
stmt: GEI2(reg,reg) "cmp r%0,r%1\nbge %a\n" 2
stmt: GEI4(reg,reg) "cmpl r%0,r%1\nbge %a\n" 2
stmt: GEU2(reg,reg) "cmp r%0,r%1\nbgeu %a\n" 2
stmt: GEU4(reg,reg) "cmpl r%0,r%1\nbgeu %a\n" 2
stmt: GTI2(reg,reg) "cmp r%0,r%1\nbgt %a\n" 2
stmt: GTI4(reg,reg) "cmpl r%0,r%1\nbgt %a\n" 2
stmt: GTU2(reg,reg) "cmp r%0,r%1\nbgtu %a\n" 2
stmt: GTU4(reg,reg) "cmpl r%0,r%1\nbgtu %a\n" 2
stmt: LEI2(reg,reg) "cmp r%0,r%1\nble %a\n" 2
stmt: LEI4(reg,reg) "cmpl r%0,r%1\nble %a\n" 2
stmt: LEU2(reg,reg) "cmp r%0,r%1\nbleu %a\n" 2
stmt: LEU4(reg,reg) "cmpl r%0,r%1\nbleu %a\n" 2
stmt: LTI2(reg,reg) "cmp r%0,r%1\nblt %a\n" 2
stmt: LTI4(reg,reg) "cmpl r%0,r%1\nblt %a\n" 2
stmt: LTU2(reg,reg) "cmp r%0,r%1\nbltu %a\n" 2
stmt: LTU4(reg,reg) "cmpl r%0,r%1\nbltu %a\n" 2
stmt: NEI2(reg,reg) "cmp r%0,r%1\nbne %a\n" 2
stmt: NEI4(reg,reg) "cmpl r%0,r%1\nbne %a\n" 2
stmt: NEU2(reg,reg) "cmp r%0,r%1\nbne %a\n" 2
stmt: NEU4(reg,reg) "cmpl r%0,r%1\nbne %a\n" 2
stmt: EQI2(reg,con) "cmpi r%0,%1\nbeq %a\n" 2
stmt: EQI4(reg,con) "cmpil r%0,%1\nbeq %a\n" 2
stmt: EQU2(reg,con) "cmpi r%0,%1\nbeq %a\n" 2
stmt: EQU4(reg,con) "cmpil r%0,%1\nbeq %a\n" 2
stmt: GEI2(reg,con) "cmpi r%0,%1\nbge %a\n" 2
stmt: GEI4(reg,con) "cmpil r%0,%1\nbge %a\n" 2
stmt: GEU2(reg,con) "cmpi r%0,%1\nbgeu %a\n" 2
stmt: GEU4(reg,con) "cmpil r%0,%1\nbgeu %a\n" 2
stmt: GTI2(reg,con) "cmpi r%0,%1\nbgt %a\n" 2
stmt: GTI4(reg,con) "cmpil r%0,%1\nbgt %a\n" 2
stmt: GTU2(reg,con) "cmpi r%0,%1\nbgtu %a\n" 2
stmt: GTU4(reg,con) "cmpil r%0,%1\nbgtu %a\n" 2
stmt: LEI2(reg,con) "cmpi r%0,%1\nble %a\n" 2
stmt: LEI4(reg,con) "cmpil r%0,%1\nble %a\n" 2
stmt: LEU2(reg,con) "cmpi r%0,%1\nbleu %a\n" 2
stmt: LEU4(reg,con) "cmpil r%0,%1\nbleu %a\n" 2
stmt: LTI2(reg,con) "cmpi r%0,%1\nblt %a\n" 2
stmt: LTI4(reg,con) "cmpil r%0,%1\nblt %a\n" 2
stmt: LTU2(reg,con) "cmpi r%0,%1\nbltu %a\n" 2
stmt: LTU4(reg,con) "cmpil r%0,%1\nbltu %a\n" 2
stmt: NEI2(reg,con) "cmpi r%0,%1\nbne %a\n" 2
stmt: NEI4(reg,con) "cmpil r%0,%1\nbne %a\n" 2
stmt: NEU2(reg,con) "cmpi r%0,%1\nbne %a\n" 2
stmt: NEU4(reg,con) "cmpil r%0,%1\nbne %a\n" 2
stmt: EQF4(reg,reg) "" fp()
stmt: LEF4(reg,reg) "" fp()
stmt: LTF4(reg,reg) "" fp()
stmt: GEF4(reg,reg) "" fp()
stmt: GTF4(reg,reg) "" fp()
stmt: NEF4(reg,reg) "" fp()
ar: ADDRGP2 "%a"
reg: CALLF4(ar) "call %0\n" fp()
reg: CALLI2(ar) "call %0\n" 1
reg: CALLI4(ar) "call %0\n" 1
reg: CALLP2(ar) "call %0\n" 1
reg: CALLU2(ar) "call %0\n" 1
reg: CALLU4(ar) "call %0\n" 1
stmt: CALLV(ar) "call %0\n" 1
ar: reg "r%0"
ar: CNSTP2 "%a" range(a, 0, 0x0ffff)
stmt: RETF4(reg) "# ret\n" fp()
stmt: RETI2(reg) "# ret\n" 1
stmt: RETI4(reg) "# ret\n" 1
stmt: RETU2(reg) "# ret\n" 1
stmt: RETU4(reg) "# ret\n" 1
stmt: RETP2(reg) "# ret\n" 1
stmt: RETV(reg) "# ret\n" 1
stmt: ARGF4(reg) "# arg\n" fp()
stmt: ARGI2(reg) "# arg\n" 1
stmt: ARGI4(reg) "# arg\n" 1
stmt: ARGP2(reg) "# arg\n" 1
stmt: ARGU2(reg) "# arg\n" 1
stmt: ARGU4(reg) "# arg\n" 1
stmt: ARGB(INDIRB(reg)) "# argb %0\n" 1
stmt: ASGNB(reg,INDIRB(reg)) "# asgnb %0 %1\n" 1
%%
static void progend(void){}
static void progbeg(int argc, char *argv[]) {
int i;
time_t now;
struct tm* ptmNow;
static char rev[] = "$Revision: 3 $";
{
union {
char c;
int i;
} u;
u.i = 0;
u.c = 1;
swap = ((int)(u.i == 1)) != IR->little_endian;
}
time(&now);
ptmNow = localtime(&now);
rev[strlen(rev)-2] = 0;
printf("; generated by lcc-xr16 rev.%s on %s\n", rev+11, asctime(ptmNow));
parseflags(argc, argv);
for (i = 0; i < argc; i++)
if (strncmp(argv[i], "-G", 2) == 0)
gnum = atoi(argv[i] + 2);
for (i = 0; i < NUM_IREGS; i++)
ireg[i] = mkreg("%d", i, 1, IREG);
ireg[REG_SP]->x.name = "sp";
for (i = 0; i < NUM_IREGS; i += 2)
lreg[i] = mkreg("%d", i, 3, IREG);
for (i = 0; i < 31; i += 2)
freg2[i] = mkreg("%d", i, 3, FREG);
r3r4 = mkreg("3", 3, 3, IREG);
r4r5 = mkreg("4", 4, 3, IREG);
freg2w = mkwildcard(freg2);
iregw = mkwildcard(ireg);
lregw = mkwildcard(lreg);
tmask[IREG] = INTTMP; tmask[FREG] = FLTTMP;
vmask[IREG] = INTVAR; vmask[FREG] = FLTVAR;
blkreg = mkreg(SZ_REG_FIRST_TEMP, REG_FIRST_TEMP, 7, IREG);
}
static Symbol rmap(int opk) {
switch (optype(opk)) {
case I: case U:
return (opsize(opk) == 4) ? lregw : iregw;
case P: case B:
return iregw;
case F:
fp();
return freg2w;
default:
return 0;
}
}
static void target(Node p) {
assert(p);
switch (specific(p->op)) {
case CNST+I: case CNST+U: case CNST+P:
if (range(p, 0, 0) == 0) {
setreg(p, ireg[0]);
p->x.registered = 1;
}
break;
case CALL+V:
break;
case CALL+F:
setreg(p, freg2[0]);
break;
case CALL+I: case CALL+P: case CALL+U:
setreg(p, ireg[REG_RETVAL]);
break;
case RET+F:
rtarget(p, 0, freg2[0]);
break;
case RET+I: case RET+U: case RET+P:
rtarget(p, 0, ireg[REG_RETVAL]);
break;
case ARG+F: case ARG+I: case ARG+P: case ARG+U: {
static int ty0;
int ty = optype(p->op);
Symbol q;
q = argreg(p->x.argno, p->syms[2]->u.c.v.i, ty, opsize(p->op), ty0);
if (p->x.argno == 0)
ty0 = ty;
if (q &&
!(ty == F && q->x.regnode->set == IREG))
rtarget(p, 0, q);
break;
}
case ASGN+B: rtarget(p->kids[1], 0, blkreg); break;
case ARG+B: rtarget(p->kids[0], 0, blkreg); break;
case DIV+I: case MOD+I: case MUL+I:
case DIV+U: case MOD+U: case MUL+U:
/* REVIEW: LSH, RSH? */
assert(REG_FIRST_ARG+1 <= REG_LAST_ARG);
setreg(p, ireg[REG_RETVAL]);
rtarget(p, 0, ireg[REG_FIRST_ARG]);
rtarget(p, 1, ireg[REG_FIRST_ARG+1]);
break;
}
}
static void clobber(Node p) {
assert(p);
switch (specific(p->op)) {
case CALL+F:
spill(INTTMP | INTRET, IREG, p);
spill(FLTTMP, FREG, p);
break;
case CALL+I: case CALL+P: case CALL+U:
spill(INTTMP, IREG, p);
spill(FLTTMP | FLTRET, FREG, p);
break;
case CALL+V:
spill(INTTMP | INTRET, IREG, p);
spill(FLTTMP | FLTRET, FREG, p);
break;
}
}
static void emit2(Node p) {
int dst, n, src, sz, ty;
static int ty0;
Symbol q;
switch (specific(p->op)) {
case ARG+F: case ARG+I: case ARG+P: case ARG+U:
ty = optype(p->op);
sz = opsize(p->op);
if (p->x.argno == 0)
ty0 = ty;
q = argreg(p->x.argno, p->syms[2]->u.c.v.i, ty, sz, ty0);
src = getregnum(p->x.kids[0]);
if (q == NULL && ty == F && sz == 4)
print("s.s rf%d,%d(sp)\n", src, p->syms[2]->u.c.v.i);
else if (q == NULL && ty == F)
print("s.d rf%d,%d(sp)\n", src, p->syms[2]->u.c.v.i);
else if (q == NULL)
print("s%c r%d,%d(sp)\n", "wl"[sz==4], src, p->syms[2]->u.c.v.i);
else if (ty == F && sz == 4 && q->x.regnode->set == IREG)
print("mfc1 r%d,rf%d\n", q->x.regnode->number, src);
else if (ty == F && q->x.regnode->set == IREG)
print("mfc1.d r%d,rf%d\n", q->x.regnode->number, src);
break;
case ASGN+B:
dalign = salign = p->syms[1]->u.c.v.i;
blkcopy(getregnum(p->x.kids[0]), 0,
getregnum(p->x.kids[1]), 0,
p->syms[0]->u.c.v.i, tmpregs);
break;
case ARG+B:
dalign = 4;
salign = p->syms[1]->u.c.v.i;
blkcopy(REG_SP, p->syms[2]->u.c.v.i,
getregnum(p->x.kids[0]), 0,
p->syms[0]->u.c.v.i, tmpregs);
n = p->syms[2]->u.c.v.i + p->syms[0]->u.c.v.i;
dst = p->syms[2]->u.c.v.i;
for ( ; dst <= (4*(NUM_ARG_REGS-1)) && dst < n; dst += 4)
print("lw r%d,%d(sp)\n", (dst/4)+4, dst);
break;
}
}
static Symbol argreg(int argno, int offset, int ty, int sz, int ty0) {
assert((offset&1) == 0);
if (offset + sz > 2*NUM_ARG_REGS || !(ty == I || ty == U || ty == P))
return NULL;
else if (argno == 0 && sz == 4)
return r3r4;
else if (argno == 1 && sz == 4)
return r4r5;
else
return ireg[(offset/2) + REG_FIRST_ARG];
}
static void doarg(Node p) {
static int argno;
int align;
if (argoffset == 0)
argno = 0;
p->x.argno = argno++;
align = p->syms[1]->u.c.v.i < 2 ? 2 : p->syms[1]->u.c.v.i;
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