📄 xr16.md
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%{
/*
* XR16 machine description file.
*
* Portions copyright (C) 1999, 2000, Gray Research LLC. All rights reserved.
* Portions of this file are subject to the XSOC License Agreement;
* you may not use them except in compliance with this Agreement.
* See the LICENSE file.
*
* This work is derived from the original src/mips.md file in the
* lcc4.1 distribution. See the CPYRIGHT file.
*
* Registers Use
* r0 zero; unchangeable
* r1 reserved for the assembler
* r2 function return value
* r3-r5 first function arg(s)
* r6-r9 scratch registers
* r10-r12 register variables
* r13 stack pointer
* r14 interrupt return address (reserved)
* r15 return address
*
* Operator terminals generated by ops c=1 s=2 i=2 l=4 h=4 f=4 d=4 x=4 p=2
*
* Floating point is not implemented.
*/
#define INTTMP 0x03C0
#define INTVAR 0x1C00
#define FLTTMP 0x000f0ff0
#define FLTVAR 0xfff00000
#define INTRET 0x0004
#define FLTRET 0x00000003
#define NUM_IREGS 16
#define REG_RETVAL 2 /* r2: return value */
#define REG_FIRST_ARG 3 /* r3: first argument register */
#define REG_LAST_ARG 5 /* r5: last argument register */
#define REG_FIRST_TEMP 6 /* r6: first temp register */
#define SZ_REG_FIRST_TEMP "6" /* r6: first temp register */
#define REG_LAST_TEMP 9 /* r9: last temp register */
#define REG_SP 13 /* r13, sp: stack pointer */
#define REG_RETADDR 15 /* r15: return address */
#define NUM_ARG_REGS (REG_LAST_ARG - REG_FIRST_ARG + 1)
#define INT_CALLEE_SAVE (INTVAR | ((unsigned)1 << REG_RETADDR))
#define readsreg(p) \
(generic((p)->op)==INDIR && (p)->kids[0]->op==VREG+P)
#define setsrc(d) ((d) && (d)->x.regnode && \
(d)->x.regnode->set == src->x.regnode->set && \
(d)->x.regnode->mask&src->x.regnode->mask)
#define relink(a, b) ((b)->x.prev = (a), (a)->x.next = (b))
#include "c.h"
#include <time.h>
#define NODEPTR_TYPE Node
#define OP_LABEL(p) ((p)->op)
#define LEFT_CHILD(p) ((p)->kids[0])
#define RIGHT_CHILD(p) ((p)->kids[1])
#define STATE_LABEL(p) ((p)->x.state)
static void address(Symbol, Symbol, long);
static void blkfetch(int, int, int, int);
static void blkloop(int, int, int, int, int, int[]);
static void blkstore(int, int, int, int);
static void defaddress(Symbol);
static void defconst(int, int, Value);
static void defstring(int, char *);
static void defsymbol(Symbol);
static void doarg(Node);
static void emit2(Node);
static void export(Symbol);
static void clobber(Node);
static void function(Symbol, Symbol [], Symbol [], int);
static void global(Symbol);
static void import(Symbol);
static void local(Symbol);
static void progbeg(int, char **);
static void progend(void);
static void segment(int);
static void space(int);
static void target(Node);
static int fp();
static int bitcount (unsigned);
static Symbol argreg (int, int, int, int, int);
static Symbol ireg[32], lreg[32], freg2[32], r3r4, r4r5;
static Symbol iregw, lregw, freg2w;
static int tmpregs[] = {1, REG_FIRST_TEMP+1, REG_FIRST_TEMP+2};
static Symbol blkreg;
static int gnum = 8;
static int cseg;
%}
%start stmt
%term CNSTF4=4113
%term CNSTI1=1045 CNSTI2=2069 CNSTI4=4117
%term CNSTP2=2071
%term CNSTU1=1046 CNSTU2=2070 CNSTU4=4118
%term ARGB=41
%term ARGF4=4129
%term ARGI2=2085 ARGI4=4133
%term ARGP2=2087
%term ARGU2=2086 ARGU4=4134
%term ASGNB=57
%term ASGNF4=4145
%term ASGNI1=1077 ASGNI2=2101 ASGNI4=4149
%term ASGNP2=2103
%term ASGNU1=1078 ASGNU2=2102 ASGNU4=4150
%term INDIRB=73
%term INDIRF4=4161
%term INDIRI1=1093 INDIRI2=2117 INDIRI4=4165
%term INDIRP2=2119
%term INDIRU1=1094 INDIRU2=2118 INDIRU4=4166
%term CVFF4=4209
%term CVFI2=2165 CVFI4=4213
%term CVIF4=4225
%term CVII1=1157 CVII2=2181 CVII4=4229
%term CVIU1=1158 CVIU2=2182 CVIU4=4230
%term CVPU2=2198
%term CVUI1=1205 CVUI2=2229 CVUI4=4277
%term CVUP2=2231
%term CVUU1=1206 CVUU2=2230 CVUU4=4278
%term NEGF4=4289
%term NEGI2=2245 NEGI4=4293
%term CALLB=217
%term CALLF4=4305
%term CALLI2=2261 CALLI4=4309
%term CALLP2=2263
%term CALLU2=2262 CALLU4=4310
%term CALLV=216
%term RETF4=4337
%term RETI2=2293 RETI4=4341
%term RETP2=2295
%term RETU2=2294 RETU4=4342
%term RETV=248
%term ADDRGP2=2311
%term ADDRFP2=2327
%term ADDRLP2=2343
%term ADDF4=4401
%term ADDI2=2357 ADDI4=4405
%term ADDP2=2359
%term ADDU2=2358 ADDU4=4406
%term SUBF4=4417
%term SUBI2=2373 SUBI4=4421
%term SUBP2=2375
%term SUBU2=2374 SUBU4=4422
%term LSHI2=2389 LSHI4=4437
%term LSHU2=2390 LSHU4=4438
%term MODI2=2405 MODI4=4453
%term MODU2=2406 MODU4=4454
%term RSHI2=2421 RSHI4=4469
%term RSHU2=2422 RSHU4=4470
%term BANDI2=2437 BANDI4=4485
%term BANDU2=2438 BANDU4=4486
%term BCOMI2=2453 BCOMI4=4501
%term BCOMU2=2454 BCOMU4=4502
%term BORI2=2469 BORI4=4517
%term BORU2=2470 BORU4=4518
%term BXORI2=2485 BXORI4=4533
%term BXORU2=2486 BXORU4=4534
%term DIVF4=4545
%term DIVI2=2501 DIVI4=4549
%term DIVU2=2502 DIVU4=4550
%term MULF4=4561
%term MULI2=2517 MULI4=4565
%term MULU2=2518 MULU4=4566
%term EQF4=4577
%term EQI2=2533 EQI4=4581
%term EQU2=2534 EQU4=4582
%term GEF4=4593
%term GEI2=2549 GEI4=4597
%term GEU2=2550 GEU4=4598
%term GTF4=4609
%term GTI2=2565 GTI4=4613
%term GTU2=2566 GTU4=4614
%term LEF4=4625
%term LEI2=2581 LEI4=4629
%term LEU2=2582 LEU4=4630
%term LTF4=4641
%term LTI2=2597 LTI4=4645
%term LTU2=2598 LTU4=4646
%term NEF4=4657
%term NEI2=2613 NEI4=4661
%term NEU2=2614 NEU4=4662
%term JUMPV=584
%term LABELV=600
%term LOADB=233
%term LOADF4=4321
%term LOADI1=1253 LOADI2=2277 LOADI4=4325
%term LOADP2=2279
%term LOADU1=1254 LOADU2=2278 LOADU4=4326
%term VREGP=711
%%
reg: INDIRI1(VREGP) "# read register\n"
reg: INDIRU1(VREGP) "# read register\n"
reg: INDIRI2(VREGP) "# read register\n"
reg: INDIRU2(VREGP) "# read register\n"
reg: INDIRF4(VREGP) "# read register\n" fp()
reg: INDIRI4(VREGP) "# read register\n"
reg: INDIRP2(VREGP) "# read register\n"
reg: INDIRU4(VREGP) "# read register\n"
stmt: ASGNI1(VREGP,reg) "# write register\n"
stmt: ASGNU1(VREGP,reg) "# write register\n"
stmt: ASGNI2(VREGP,reg) "# write register\n"
stmt: ASGNU2(VREGP,reg) "# write register\n"
stmt: ASGNP2(VREGP,reg) "# write register\n"
stmt: ASGNF4(VREGP,reg) "# write register\n" fp()
stmt: ASGNI4(VREGP,reg) "# write register\n"
stmt: ASGNU4(VREGP,reg) "# write register\n"
con: CNSTI1 "%a"
con: CNSTU1 "%a"
con: CNSTI2 "%a"
con: CNSTU2 "%a"
con: CNSTP2 "%a"
reg: CNSTI4 "leal r%c,%a\n" 2
reg: CNSTU4 "leal r%c,%a\n" 2
stmt: reg ""
acon: con "%0"
acon: ADDRGP2 "%a"
addr: ADDI2(reg,acon) "%1(r%0)"
addr: ADDU2(reg,acon) "%1(r%0)"
addr: ADDP2(reg,acon) "%1(r%0)"
addr: acon "%0"
addr: reg "(r%0)"
addr: ADDRFP2 "%a+%F(sp)"
addr: ADDRLP2 "%a+%F(sp)"
reg: addr "lea r%c,%0\n" 1
reg: CNSTI1 "# reg\n" range(a, 0, 0)
reg: CNSTI2 "# reg\n" range(a, 0, 0)
reg: CNSTI4 "# reg\n" range(a, 0, 0)
reg: CNSTU1 "# reg\n" range(a, 0, 0)
reg: CNSTU2 "# reg\n" range(a, 0, 0)
reg: CNSTU4 "# reg\n" range(a, 0, 0)
reg: CNSTP2 "# reg\n" range(a, 0, 0)
stmt: ASGNI1(addr,reg) "sb r%1,%0\n" 1
stmt: ASGNU1(addr,reg) "sb r%1,%0\n" 1
stmt: ASGNI2(addr,reg) "sw r%1,%0\n" 1
stmt: ASGNU2(addr,reg) "sw r%1,%0\n" 1
stmt: ASGNI4(addr,reg) "sl r%1,%0\n" 1
stmt: ASGNU4(addr,reg) "sl r%1,%0\n" 1
stmt: ASGNP2(addr,reg) "sw r%1,%0\n" 1
reg: INDIRI1(addr) "lbs r%c,%0\n" 1
reg: INDIRU1(addr) "lb r%c,%0\n" 1
reg: INDIRI2(addr) "lw r%c,%0\n" 1
reg: INDIRU2(addr) "lw r%c,%0\n" 1
reg: INDIRI4(addr) "ll r%c,%0\n" 1
reg: INDIRU4(addr) "ll r%c,%0\n" 1
reg: INDIRP2(addr) "lw r%c,%0\n" 1
reg: CVII2(INDIRI1(addr)) "lbs r%c,%0\n" 1
reg: CVUU2(INDIRU1(addr)) "lb r%c,%0\n" 1
reg: CVUI2(INDIRU1(addr)) "lb r%c,%0\n" 1
reg: CVII4(INDIRI1(addr)) "lbsl r%c,%0\n" 1
reg: CVII4(INDIRI2(addr)) "lwsl r%c,%0\n" 1
reg: CVUU4(INDIRU1(addr)) "lbul r%c,%0\n" 1
reg: CVUU4(INDIRU2(addr)) "lwul r%c,%0\n" 1
reg: CVUI4(INDIRU1(addr)) "lbul r%c,%0\n" 1
reg: CVUI4(INDIRU2(addr)) "lwul r%c,%0\n" 1
reg: INDIRF4(addr) "# fp\n" fp()
stmt: ASGNF4(addr,reg) "# fp\n" fp()
reg: DIVI2(reg,reg) "call _divi2\n" 1
reg: DIVI4(reg,reg) "call _divi4\n" 1
reg: DIVU2(reg,reg) "call _divu2\n" 1
reg: DIVU4(reg,reg) "call _divu4\n" 1
reg: MODI2(reg,reg) "call _modi2\n" 1
reg: MODI4(reg,reg) "call _modi4\n" 1
reg: MODU2(reg,reg) "call _modu2\n" 1
reg: MODU4(reg,reg) "call _modu4\n" 1
reg: MULI2(reg,reg) "call _muli2\n" 1
reg: MULI4(reg,reg) "call _muli4\n" 1
reg: MULU2(reg,reg) "call _mulu2\n" 1
reg: MULU4(reg,reg) "call _mulu4\n" 1
reg: ADDI2(reg,reg) "add r%c,r%0,r%1\n" 1
reg: ADDI4(reg,reg) "addl r%c,r%0,r%1\n" 1
reg: ADDP2(reg,reg) "add r%c,r%0,r%1\n" 1
reg: ADDU2(reg,reg) "add r%c,r%0,r%1\n" 1
reg: ADDU4(reg,reg) "addl r%c,r%0,r%1\n" 1
reg: BANDI2(reg,reg) "?mov r%c,r%0\nand r%c,r%1\n" 1
reg: BANDI4(reg,reg) "?movl r%c,r%0\nandl r%c,r%1\n" 1
reg: BORI2(reg,reg) "?mov r%c,r%0\nor r%c,r%1\n" 1
reg: BORI4(reg,reg) "?movl r%c,r%0\norl r%c,r%1\n" 1
reg: BXORI2(reg,reg) "?mov r%c,r%0\nxor r%c,r%1\n" 1
reg: BXORI4(reg,reg) "?movl r%c,r%0\nxorl r%c,r%1\n" 1
reg: BANDU2(reg,reg) "?mov r%c,r%0\nand r%c,r%1\n" 1
reg: BANDU4(reg,reg) "?movl r%c,r%0\nandl r%c,r%1\n" 1
reg: BORU2(reg,reg) "?mov r%c,r%0\nor r%c,r%1\n" 1
reg: BORU4(reg,reg) "?movl r%c,r%0\norl r%c,r%1\n" 1
reg: BXORU2(reg,reg) "?mov r%c,r%0\nxor r%c,r%1\n" 1
reg: BXORU4(reg,reg) "?movl r%c,r%0\nxorl r%c,r%1\n" 1
reg: SUBI2(reg,reg) "sub r%c,r%0,r%1\n" 1
reg: SUBI4(reg,reg) "subl r%c,r%0,r%1\n" 1
reg: SUBP2(reg,reg) "sub r%c,r%0,r%1\n" 1
reg: SUBU2(reg,reg) "sub r%c,r%0,r%1\n" 1
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