xr16.s

This free cpu-ip! use verilog

; xr16.s -- simple xr16 test suite
; 
; Copyright (C) 1999, 2000, Gray Research LLC.  All rights reserved.
; The contents of this file are subject to the XSOC License Agreement;
; you may not use this file except in compliance with this Agreement.
; See the LICENSE file.

; $Header: /dist/tests/xr16.s 4     4/03/00 9:04p Jan $

; do not edit the next 10 lines w/o understanding of the hand assembled
; stores to w, and calls to return, in the branch and jump annul tests below.

; br
reset:
	br l10
	jal r2,error
ok:
	mov r2,r0
	j reset
w:
	word 0
w2:
	word 0
align 16
error:
	j reset

; cmp/beq
l10:
	cmp r0,r0
	beq l20
e10:
	jal r2,error

; cmp/bne
l20:
	cmp r0,r0
	bne e20
	cmpi r0,0
	bne e20
	br l30
e20:
	jal r2,error

; addi
l30:
	addi r1,r0,1
	addi r2,r0,1
	cmp r1,r2
	bne e30
	cmp r2,r1
	bne e30
	cmp r1,r0
	beq e30
	cmp r0,r1
	beq e30
	cmp r2,r0
	beq e30
	cmp r0,r2
	beq e30
	br l40
e30:
	jal r2,error

; add
l40:
	addi r1,r0,1
	addi r2,r0,1
	addi r3,r0,2
	cmp r1,r2
	bne e40
	cmp r1,r3
	beq e40
	cmp r2,r3
	beq e40
	add r4,r1,r2
	cmp r4,r3
	bne e40
	br l50
e40:
	jal r2,error

; sub
l50:
	addi r1,r0,1
	addi r2,r0,1
	addi r3,r0,2
	sub r4,r3,r2
	cmp r4,r1
	bne e50
	sub r4,r4,r2
	cmp r4,r0
	bne e50
	cmp r1,r2
	bne e50
	cmp r1,r3
	beq e50
	cmp r2,r3
	beq e50
	add r4,r1,r2
	cmp r4,r3
	bne e50
	br l55
e50:
	jal r2,error

; registers
l55:
	addi r1,r0,1
	add r2,r1,r1
	add r3,r2,r2
	add r4,r3,r3
	add r5,r4,r4
	add r6,r5,r5
	add r7,r6,r6
	add r8,r7,r7
	add r9,r8,r8
	add r10,r9,r9
	add r11,r10,r10
	add r12,r11,r11
	add r13,r12,r12
	add r14,r13,r13
	add r15,r14,r14
	cmpi r1,1
	bne e55
	cmpi r2,2
	bne e55
	cmpi r3,4
	bne e55
	cmpi r4,8
	bne e55
	cmpi r5,0x10
	bne e55
	cmpi r6,0x20
	bne e55
	cmpi r7,0x40
	bne e55
	cmpi r8,0x80
	bne e55
	cmpi r9,0x100
	bne e55
	cmpi r10,0x200
	bne e55
	cmpi r11,0x400
	bne e55
	cmpi r12,0x800
	bne e55
	cmpi r13,0x1000
	bne e55
	cmpi r14,0x2000
	bne e55
	cmpi r15,0x4000
	bne e55
	br t_add
e55:
	jal r2,error

; add
t_add:
	lea r1,1
	lea r2,1
	add r3,r1,r2
	cmpi r3,2
	bne e_add
	lea r1,0x8000
	lea r2,0x8000
	add r3,r1,r2
	cmpi r3,0
	bne e_add

	lea r1,2
	lea r2,-1
	add r3,r2,r1
	add r4,r1,r2
	cmpi r3,1
	bne e_add
	cmp r3,r4
	bne e_add

	lea r1,-2
	lea r2,1
	add r3,r2,r1
	add r4,r1,r2
	cmpi r3,-1
	bne e_add
	cmp r3,r4
	bne e_add

	lea r1,-2
	lea r2,-1
	add r3,r2,r1
	add r4,r1,r2
	cmpi r3,-3
	bne e_add
	cmp r3,r4
	bne e_add
	br t_sub
e_add:
	jal r2,error

; sub
t_sub:
	lea r1,1
	lea r2,1
	sub r3,r1,r2
	cmpi r3,0
	bne e_sub
	lea r1,0x8000
	lea r2,0x8000
	sub r3,r1,r2
	cmpi r3,0
	bne e_sub

	lea r1,2
	lea r2,-1
	sub r3,r2,r1
	sub r4,r1,r2
	sub r4,r0,r4
	cmpi r3,-3
	bne e_sub
	cmp r3,r4
	bne e_sub

	lea r1,-2
	lea r2,1
	sub r3,r2,r1
	sub r4,r1,r2
	sub r4,r0,r4
	cmpi r3,3
	bne e_sub
	cmp r3,r4
	bne e_sub

	lea r1,-2
	lea r2,-1
	sub r3,r2,r1
	sub r4,r1,r2
	sub r4,r0,r4
	cmpi r3,1
	bne e_sub
	cmp r3,r4
	bne e_sub
	br t_addi
e_sub:
	jal r2,error

; addi
t_addi:
	addi r1,r0,1
	addi r1,r1,2
	addi r1,r1,4
	addi r1,r1,8
	addi r1,r1,0x10
	addi r1,r1,0x20
	addi r1,r1,0x40
	addi r1,r1,0x80
	addi r1,r1,0x100
	addi r1,r1,0x200
	addi r1,r1,0x400
	addi r1,r1,0x800
	addi r1,r1,0x1000
	addi r1,r1,0x2000
	addi r1,r1,0x4000
	addi r1,r1,0x8000
	cmpi r1,-1
	bne e_addi
	subi r1,r0,1
	subi r1,r1,2
	subi r1,r1,4
	subi r1,r1,8
	subi r1,r1,0x10
	subi r1,r1,0x20
	subi r1,r1,0x40
	subi r1,r1,0x80
	subi r1,r1,0x100
	subi r1,r1,0x200
	subi r1,r1,0x400
	subi r1,r1,0x800
	subi r1,r1,0x1000
	subi r1,r1,0x2000
	subi r1,r1,0x4000
	lea r2,0x8000
	sub r1,r1,r2
	cmpi r1,1
	bne e_addi
	addi r1,r0,1
	addi r2,r0,1
	add r3,r2,r1
	add r4,r3,r2
	add r5,r4,r3
	add r6,r5,r4
	add r7,r6,r5
	add r8,r7,r6
	add r9,r8,r7
	add r10,r9,r8
	add r11,r10,r9
	add r12,r11,r10
	add r13,r12,r11
	add r14,r13,r12
	add r15,r14,r13
	add r1,r15,r14
	add r2,r1,r15
	add r3,r2,r1
	add r4,r3,r2
	add r5,r4,r3
	add r6,r5,r4
	add r7,r6,r5
	add r8,r7,r6
	add r9,r8,r7
	add r10,r9,r8
	add r11,r10,r9
	add r12,r11,r10
	add r13,r12,r11
	add r14,r13,r12
	add r15,r14,r13
	add r1,r15,r14
	add r2,r1,r15
	add r3,r2,r1
	add r4,r3,r2
	add r5,r4,r3
	add r6,r5,r4
	add r7,r6,r5
	add r8,r7,r6
	add r9,r8,r7
	add r10,r9,r8
	add r11,r10,r9
	add r12,r11,r10
	add r13,r12,r11
	add r14,r13,r12
	add r15,r14,r13
	cmpi r15,16258
	bne e_addi
	br t_log
e_addi:
	jal r2,error

; and/or/xor/andn
t_log:
	lea r1,1

	mov r2,r0
	and r2,r0
	cmpi r2,0
	bne e_log
	mov r2,r0
	or r2,r0
	cmpi r2,0
	bne e_log
	mov r2,r0
	xor r2,r0
	cmpi r2,0
	bne e_log
	mov r2,r0
	andn r2,r0
	cmpi r2,0
	bne e_log

	mov r2,r1
	and r2,r0
	cmpi r2,0
	bne e_log
	mov r2,r1
	or r2,r0
	cmpi r2,1
	bne e_log
	mov r2,r1
	xor r2,r0
	cmpi r2,1
	bne e_log
	mov r2,r1
	andn r2,r0
	cmpi r2,1
	bne e_log

	mov r2,r0
	and r2,r1
	cmpi r2,0
	bne e_log
	mov r2,r0
	or r2,r1
	cmpi r2,1
	bne e_log
	mov r2,r0
	xor r2,r1
	cmpi r2,1
	bne e_log
	mov r2,r0
	andn r2,r1
	cmpi r2,0
	bne e_log

	mov r2,r1
	and r2,r1
	cmpi r2,1
	bne e_log
	mov r2,r1
	or r2,r1
	cmpi r2,1
	bne e_log
	mov r2,r1
	xor r2,r1
	cmpi r2,0
	bne e_log
	mov r2,r1
	andn r2,r1
	cmpi r2,0
	bne e_log
	br t_log2
e_log:
	jal r2,error

t_log2:
	lea r1,0x5555
	lea r2,0xAAAA

	mov r3,r1
	and r3,r1
	cmp r3,r1
	bne e_log2
	mov r3,r1
	or r3,r1
	cmp r3,r1
	bne e_log2
	mov r3,r1
	xor r3,r1
	cmpi r3,0
	bne e_log2
	mov r3,r1
	andn r3,r1
	cmpi r3,0
	bne e_log2

	mov r3,r2
	and r3,r1
	cmpi r3,0
	bne e_log2
	mov r3,r2
	or r3,r1
	cmpi r3,-1
	bne e_log2
	mov r3,r2
	xor r3,r1
	cmpi r3,-1
	bne e_log2
	mov r3,r2
	andn r3,r1
	cmp r3,r2
	bne e_log2

	mov r3,r1
	and r3,r2
	cmpi r3,0
	bne e_log2
	mov r3,r1
	or r3,r2
	cmpi r3,-1
	bne e_log2
	mov r3,r1
	xor r3,r2
	cmpi r3,-1
	bne e_log2
	mov r3,r1
	andn r3,r2
	cmp r3,r1
	bne e_log2

	mov r3,r2
	and r3,r2
	cmp r3,r2
	bne e_log2
	mov r3,r2
	or r3,r2
	cmp r3,r2
	bne e_log2
	mov r3,r2
	xor r3,r2
	cmpi r3,0
	bne e_log2
	mov r3,r2
	andn r3,r2
	cmpi r3,0
	bne e_log2
	br t_log3
e_log2:
	jal r2,error

t_log3:
	lea r1,0xF0F0
	lea r2,0x5555

	mov r3,r1
	and r3,r1
	cmp r3,r1
	bne e_log3
	mov r3,r1
	or r3,r1
	cmp r3,r1
	bne e_log3
	mov r3,r1
	xor r3,r1
	cmpi r3,0
	bne e_log3
	mov r3,r1
	andn r3,r1
	cmpi r3,0
	bne e_log3

	mov r3,r2
	and r3,r1
	cmpi r3,0x5050
	bne e_log3
	mov r3,r2
	or r3,r1
	cmpi r3,0xF5F5
	bne e_log3
	mov r3,r2
	xor r3,r1
	cmpi r3,0xA5A5
	bne e_log3
	mov r3,r2
	andn r3,r1
	cmpi r3,0x0505
	bne e_log3

	mov r3,r1
	and r3,r2
	cmpi r3,0x5050
	bne e_log3
	mov r3,r1
	or r3,r2
	cmpi r3,0xF5F5
	bne e_log3
	mov r3,r1
	xor r3,r2
	cmpi r3,0xA5A5
	bne e_log3
	mov r3,r1
	andn r3,r2
	cmpi r3,0xA0A0
	bne e_log3

	mov r3,r2
	and r3,r2
	cmp r3,r2
	bne e_log3
	mov r3,r2
	or r3,r2
	cmp r3,r2
	bne e_log3
	mov r3,r2
	xor r3,r2
	cmpi r3,0
	bne e_log3
	mov r3,r2
	andn r3,r2
	cmpi r3,0
	bne e_log3
	br t_logi
e_log3:
	jal r2,error

; andi/ori/xori/andni
t_logi:
	lea r1,1

	mov r2,r0
	andi r2,0
	cmpi r2,0
	bne e_logi
	mov r2,r0
	ori r2,0
	cmpi r2,0
	bne e_logi
	mov r2,r0
	xori r2,0
	cmpi r2,0
	bne e_logi
	mov r2,r0
	andni r2,0
	cmpi r2,0
	bne e_logi

	mov r2,r1
	andi r2,0
	cmpi r2,0
	bne e_logi
	mov r2,r1
	ori r2,0
	cmpi r2,1
	bne e_logi
	mov r2,r1
	xori r2,0
	cmpi r2,1
	bne e_logi
	mov r2,r1
	andni r2,0
	cmpi r2,1
	bne e_logi

	mov r2,r0
	andi r2,1
	cmpi r2,0
	bne e_logi
	mov r2,r0
	ori r2,1
	cmpi r2,1
	bne e_logi
	mov r2,r0
	xori r2,1
	cmpi r2,1
	bne e_logi
	mov r2,r0
	andni r2,1
	cmpi r2,0
	bne e_logi

	mov r2,r1
	andi r2,1
	cmpi r2,1
	bne e_logi
	mov r2,r1
	ori r2,1
	cmpi r2,1
	bne e_logi
	mov r2,r1
	xori r2,1
	cmpi r2,0
	bne e_logi
	mov r2,r1
	andni r2,1
	cmpi r2,0
	bne e_logi
	br t_logi2
e_logi:
	jal r2,error

t_logi2:
	lea r1,0x5555
	lea r2,0xAAAA

	mov r3,r1
	andi r3,0x5555
	cmp r3,r1
	bne e_logi2
	mov r3,r1
	ori r3,0x5555
	cmp r3,r1
	bne e_logi2
	mov r3,r1
	xori r3,0x5555
	cmpi r3,0
	bne e_logi2
	mov r3,r1
	andni r3,0x5555
	cmpi r3,0
	bne e_logi2

	mov r3,r2
	andi r3,0x5555
	cmpi r3,0
	bne e_logi2
	mov r3,r2
	ori r3,0x5555
	cmpi r3,-1
	bne e_logi2
	mov r3,r2
	xori r3,0x5555
	cmpi r3,-1
	bne e_logi2
	mov r3,r2
	andni r3,0x5555
	cmp r3,r2
	bne e_logi2

	mov r3,r1
	andi r3,0xAAAA
	cmpi r3,0
	bne e_logi2
	mov r3,r1
	ori r3,0xAAAA
	cmpi r3,-1
	bne e_logi2
	mov r3,r1
	xori r3,0xAAAA
	cmpi r3,-1
	bne e_logi2
	mov r3,r1
	andni r3,0xAAAA
	cmp r3,r1
	bne e_logi2

	mov r3,r2
	andi r3,0xAAAA
	cmp r3,r2
	bne e_logi2
	mov r3,r2
	ori r3,0xAAAA
	cmp r3,r2
	bne e_logi2
	mov r3,r2
	xori r3,0xAAAA
	cmpi r3,0
	bne e_logi2
	mov r3,r2
	andni r3,0xAAAA
	cmpi r3,0
	bne e_logi2
	br t_logi3
e_logi2:
	jal r2,error

t_logi3:
	lea r1,0xF0F0
	lea r2,0x5555

	mov r3,r1
	andi r3,0xF0F0
	cmp r3,r1
	bne e_logi3
	mov r3,r1
	ori r3,0xF0F0
	cmp r3,r1
	bne e_logi3
	mov r3,r1
	xori r3,0xF0F0
	cmpi r3,0
	bne e_logi3
	mov r3,r1
	andni r3,0xF0F0
	cmpi r3,0
	bne e_logi3

	mov r3,r2
	andi r3,0xF0F0
	cmpi r3,0x5050
	bne e_logi3
	mov r3,r2
	ori r3,0xF0F0
	cmpi r3,0xF5F5
	bne e_logi3
	mov r3,r2
	xori r3,0xF0F0
	cmpi r3,0xA5A5
	bne e_logi3
	mov r3,r2
	andni r3,0xF0F0
	cmpi r3,0x0505
	bne e_logi3

	mov r3,r1
	andi r3,0x5555
	cmpi r3,0x5050
	bne e_logi3
	mov r3,r1
	ori r3,0x5555
	cmpi r3,0xF5F5
	bne e_logi3
	mov r3,r1
	xori r3,0x5555
	cmpi r3,0xA5A5
	bne e_logi3
	mov r3,r1
	andni r3,0x5555
	cmpi r3,0xA0A0
	bne e_logi3

	mov r3,r2
	andi r3,0x5555
	cmp r3,r2
	bne e_logi3
	mov r3,r2
	ori r3,0x5555
	cmp r3,r2
	bne e_logi3
	mov r3,r2
	xori r3,0x5555
	cmpi r3,0
	bne e_logi3
	mov r3,r2
	andni r3,0x5555
	cmpi r3,0
	bne e_logi3
;	br l190
	br t_slli
e_logi3:
	jal r2,error

; ; adc/sbc/adci/sbci
; l190:
; 	lea r1,0xFFFF
; 	mov r2,r1
; 	mov r3,r1
; 	mov r4,r1
; 	addi r1,r1,1
; 	adc r2,r0
; 	adc r3,r0
; 	adc r4,r0
; 	cmpi r3,0
; 	bne e190
; 
; 	subi r1,r1,1
; 	sbc r2,r0
; 	sbc r3,r0
; 	sbc r4,r0
; 	cmpi r4,-1
; 	bne e190
; 
; 	addi r1,r1,1
; 	adci r2,0
; 	adci r3,0
; 	adci r4,0
; 	cmpi r3,0
; 	bne e190
; 
; 	subi r1,r1,1
; 	sbci r2,0
; 	sbci r3,0
; 	sbci r4,0
; 	cmpi r4,-1
; 	bne e190
; 	j reset
; e190:
; 	jal r2,error

t_slli:
	lea r1,1
	slli r1,1
	cmpi r1,2
	bne e_slli
	slli r1,1
	cmpi r1,4
	bne e_slli
	slli r1,1
	cmpi r1,8
	bne e_slli
	slli r1,1
	cmpi r1,0x10
	bne e_slli
	slli r1,1
	cmpi r1,0x20
	bne e_slli
	slli r1,1
	cmpi r1,0x40
	bne e_slli
	slli r1,1
	cmpi r1,0x80
	bne e_slli
	slli r1,1
	cmpi r1,0x100
	bne e_slli
	slli r1,1
	cmpi r1,0x200
	bne e_slli
	slli r1,1
	cmpi r1,0x400
	bne e_slli
	slli r1,1
	cmpi r1,0x800
	bne e_slli
	slli r1,1
	cmpi r1,0x1000
	bne e_slli
	slli r1,1
	cmpi r1,0x2000
	bne e_slli
	slli r1,1
	cmpi r1,0x4000
	bne e_slli
	slli r1,1
	lea r2,0x8000
	cmp r2,r1