tb_divfre.vhd

数字频率计~ VHDL 实现 可以实现频率的测量和现实的功能 8位

library  ieee;
use ieee.std_logic_1164.all;

entity tb_divfre is end;

architecture behav of tb_divfre is
   component divfre
      generic(rate: integer range 0 to 255 :=10);
      port(fin:in std_logic;fout:out std_logic);
   end component;   
   signal fi,fo : std_logic;
begin  
   uut : divfre generic map (rate=>23) port map (fin=>fi,fout=>fo); 
   process
   begin 
      fi <= '1';
      wait for 100 ns;
      fi <= '0';
      wait for 100 ns;      
   end process;
end behav;