tb_cnt10.vhd

来自「数字频率计~ VHDL 实现 可以实现频率的测量和现实的功能 8位」· VHDL 代码 · 共 34 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity tb_cnt10 is end;

architecture behav of tb_cnt10 is
   component cnt10
      port(clk:in std_logic;
           clr:in std_logic;
           ena:in std_logic;    --  jishu  ennable
            cq:out std_logic_vector(3 downto 0);  --4wei ji shu jie guo
      carryout:out std_logic);  -- jin wei shu chu
   end component;
   signal clk,clr,ena,co : std_logic;
   signal qq : std_logic_vector(3 downto 0);
begin
   dut : cnt10 port map (clk=>clk,clr=>clr,ena=>ena,cq=>qq,carryout=>co);
   process
   begin
      clk <= '0';
      wait for 10 ns;
      clk <= '1';
      wait for 10 ns;
   end process;
   process
   begin
      clr <= '1';
      ena <= '1';
      wait for 53 ns;
      clr <= '0';
      wait;
   end process;
end;